Woosung Choi

Coupled drift-diffusion (DD) and multi-subband Boltzmann transport equation (MSBTE) solver for 3D multi-gate transistors

This paper presents a self-consistent coupled DD/MSBTE solver for the device simulation of realistic 3D multi-gate transistors. The MSBTE for quasi-1D k-space is solved in the channel region while the DD equation is solved in the source/drain regions with an appropriate boundary condition at the DD/MSBTE region interfaces. In the MSBTE region, 2D Schrödinger equation with the two (electrons) or six (holes) band k · p Hamiltonian is solved to obtain the subband structure for arbitrary crystal orientations and stress conditions. Phonon and surface roughness scattering processes are taken into account in the MSBTE where the surface roughness scattering model has been extended to consider arbitrary cross-sections. Silicon nanowire transistors are considered as an application.

Performance evaluation of InGaAs, Si, and Ge nFinFETs based on coupled 3D drift-diffusion/multisubband boltzmann transport equations solver

This paper presents a simulation study of InGaAs, Si, and Ge nFinFETs by solving the coupled drift-diffusion (DD) and the multisubband Boltzmann transport equation (MSBTE) in 3D domains. The effects of the quasi-ballistic transport, source/drain contact resistances, and band-to-band tunneling (BTBT) on the device performance are studied.

General Geometric Fluctuation Modeling for Device Variability Analysis

We propose a new modeling approach based on the impedance field method (IFM) to analyze the general geometric variations in device simulations. Compared with the direct modeling of multiple variational devices, the proposed geometric variation (GV) model shows a better efficiency thanks to its IFM-based nature. Compared with the existing random geometric fluctuation (RGF) model where the noise sources are limited to the interfaces, the present GV model provides better accuracy and wider application areas as it transforms the geometric variation into global mesh deformation and computes the noise sources induced by the geometric variation in the whole simulation domain. GV model also provides great insights into the device by providing the effective noise sources, equationwise contributions, and sensitivity maps that are useful for device characterization and optimization.

In 0.53 Ga 0.47 As-Based nMOSFET Design for Low Standby Power Applications

III-V n-channel MOSFETs based on InxGa1-xAs are evaluated for low-power (LP) technology at a sub-10-nm technology node. Aggressive design rules are followed, while industry-relevant FinFET architecture is selected. We show, for the first time, quantum confinement-related leakage and performance tradeoff done self-consistently in performance evaluation using an in-house developed semiclassical tool. In this paper, we focus on In0.53Ga0.47As as the channel material, as it has been investigated heavily in the literature. Furthermore, it has a bulk bandgap EG similar to that of Ge, another highly studied complementary p-FET channel material. Higher In-content results in lower EG and hence larger band-to-band tunneling (BTBT) current, resulting in more stringent design requirements for LP applications. A comparison is done with the state-of-the-art tensile-Si (t-Si) technology, with roughly 2-GPa stress, under similar constraints LG, design rules). Thus, we show that while for 0.75 V operation, In0.53Ga0.47 As performance is limited by the BTBT and fails to outperform t-Si, it starts to perform better than t-Si below 0.7 V. VDD scaling further results in an increased performance gap between the two material systems.

Physical understanding of alloy scattering in SiGe channel for high-performance strained pFETs

For devices beyond the 14nm node, it is important to investigate performance boosters such as high mobility channels. Although pure Ge offers a higher hole mobility than Si, conventional problems like surface passivation and its integration with Si makes SiGe alloy with low Ge mole fraction a viable option. The significance of alloy scattering, however, has been widely debated [1-3], so the accurate modeling of alloy scattering in SiGe channel has become an important issue to predict the performance of future SiGe-based FETs. Usually, the calculation of alloy scattering mobility assumes an alloy scattering center in a simple analytical form with some fitting parameters, which is a good practical approach but has a limited predictability. In this paper, an atomistic tight-binding simulation is used to study alloy scattering in SiGe-based FETs, and to compare with experimental data. We conclude (i) although it is essentially impossible to avoid alloy scattering in SiGe material, (ii) high-mobility is indeed achieved in SiGe channel by combining lattice-mismatch stresses from Si virtual substrate with stresses from Source/Drain(SD) stressor.

A new kinetic lattice Monte Carlo modeling framework for the source-drain selective epitaxial growth process

We have developed a new kinetic lattice Monte Carlo modeling framework for Si/Ge selective epitaxial growth based on neighbor binding interactions within the third-nearest-neighbor range of the diamond lattice. We find that first- and second-nearest-neighbor interactions contribute significantly to the faceting between {100} and {111}, while the third-nearest-neighbor interaction is the cause of {311} facet formation. The second-nearest-neighbor interaction also facilitates lateral growth and island formation within a plane. The simulated growth kinetics and shapes are in good agreement with experimental data.

Performance evaluation of FinFETs: From multisubband BTE to DD calibration

This paper presents a hierarchical approach to link the advanced multisubband Boltzmann transport equation (MSBTE) solver to the conventional drift-diffusion (DD) model for performance evaluation of non-planar transistors in logic technology development. An automated, physics-based procedure to extract the DD model parameter set from the MSBTE simulation is described. An update on the surface roughness scattering model valid for finite barriers is also shown. As an application, the MSBTE to DD calibration is performed for a silicon nanowire transistor. The calibrated parameter set is applied to a dual channel nanowire transistor, and the effects of the source/drain series and contact resistances are studied.

Comprehensive Simulation Study of Direct Source-to-Drain Tunneling in Ultra-Scaled Si, Ge, and III-V DG-FETs

As the scaling of transistors approaches the 7-/5-nm technology nodes, direct source-to-drain tunneling (SDT) is becoming increasingly important with the shrinking gate lengths. In this paper, we present a comprehensive simulation study on the effects of SDT in ultrascaled FETs with various channel materials (Si, Ge, SiGe, InGaAs, and so on), surface/channel orientation configurations, gate lengths, body thicknesses, doping concentrations, stress levels, and temperatures. The nonequilibrium Green’s function formalism with the atomistic tight-binding basis is used to accurately model both the quantum-mechanical tunneling and the bandstructure effects. To quantify the strength of SDT, we propose a current ratio (

Multi-domain compact modeling for GeSbTe-based memory and selector devices and simulation for large-scale 3-D cross-point memory arrays

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Physics-based compact modeling framework for state-of-the-art and emerging STT-MRAM technology

), which essentially illustrates the difference between a full quantum transport model and a semiclassical model for calculating the FET OFF-current. The results clearly show that SDT strongly depends on orientations and stress levels in the FET channel, and for materials with a small transport effective-mass (e.g., Ge and InAs), SDT dominates the total OFF-current, making it difficult to achieve a low OFF-current target at a scaled gate length. In addition, it is found that the temperature dependence of the FET OFF-current decreases with the strength of SDT, which may have an implication on the technology definition and device targeting for the 7-/5-nm nodes.