Eunseok Song

Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs

In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth limitation of the conventional decoupling capacitor solutions in three-dimensional-integrated circuits (3-D-ICs), as exhibited by expensive on-chip metal-oxide-semiconductor (MOS) decoupling capacitors and inductive off-chip discrete decoupling capacitors. In particular, in comparison to the on-chip decoupling solutions, such as MOS, metal-insulator-metal and deep trench capacitors, the proposed TSV-based DCSC represents several advantages, such as small leakage currents, large capacitances ranging from tens of nF to a few μF, low equivalent series inductance (ESL) with tens of pH, and high flexibility in TSV arrangements. The proposed TSV-based DCSC can be applied by mounting decoupling capacitors, such as Si-based MOS capacitors and discrete capacitors, on the backside of a chip and connecting the capacitors to the on-chip power delivery network (PDN) through TSVs. To demonstrate the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) of the TSV-based DCSC with those of the well-known conventional decoupling capacitor methods. The TSV-based DCSC was found to exhibit the advantages of both low on-chip level ESL (under several tens of pH) and high off-chip level capacitance (up to several μF). Additionally, the PDN impedance properties of the TSV-based DCSC were analyzed with respect to the variations in the number of power/ground TSV pairs, on-chip PDN size, and capacitance values of the stacked off-chip discrete decoupling capacitors using the segmentation method.

Electromagnetic interference reduction method from handheld resonant magnetic field charger (HH-RMFC) for electric vehicle

The proposed handheld resonant magnetic field charger (HH-RMFC) is a convenient method of charging batteries in electric vehicle (EV) without any electrical contact. With close distance between Tx and Rx windings, high mutual inductance causes large reflected impedance seen by the power source. The large reflected impedance can cause distortion of current flowing through Tx and Rx windings. In frequency-domain, the distortion of current produces large current harmonics, which may have electromagnetic compatibility (EMC) issues caused by leakage magnetic field. To quantify the distortion of current, the total harmonic distortion (THD) is used. In this paper, the design method for low EMI from the HH-RMFC for EV are proposed and verified using a circuit simulator. The circuit simulation results show that THD of Tx and Rx current is below 5% using proposed method.

Measurement and analysis of voltage transfer ratio (VTR) of package-level WPT considering PDN conditions

In this study, a three dimensional multi-helix inductor design with a size smaller than 10mm×10mm is proposed for package-level wireless power transfer (WPT) using magnetic resonance, and the performance of an inductor-to-inductor voltage transfer ratio (VTR) of 70.1 % is presented. The effect of the power distribution network (PDN) load impedance on the VTR is studied and verified through measurement of the fabricated package-level WPT system. The PDN conditions consist of a power/ground (P/G) plane and various decoupling capacitors with different capacitances (10 nF, 100 nF, and 1 μF). The PDN impedance of the receiver package exhibits resonant frequencies that depend on the stack-up and dimension of the power/ground planes and also the capacitances and the locations of the decoupling capacitors. As the resonance frequency of the WPT system approaches the resonance frequency of the PDN connected to the end of the WPT system as a load, the VTR efficiency rapidly decreases. In addition, the VTR performance of the package-level WPT system can be further improved to a maximum of 18.84 % with the insertion of ferrite sheets.

Decoupling capacitor stacked chip (DCSC) in TSV-based 3D-ICs

In this paper, we introduce a new decoupling capacitor stacked chip (DCSC) with discrete capacitors and through-silicon-vias (TSVs) that can overcome the limitations of the conventional decoupling capacitor solutions such as expensive on-chip NMOS capacitor and package-level discrete decoupling capacitor with narrow-band. The key idea of the proposed TSV-based DCSC is mounting the decoupling capacitors such as silicon-based NMOS capacitor and discrete capacitor on the backside of a chip and connecting the capacitors to the on-chip PDN through TSVs. Therefore, the TSV-based DCSC provides the lowest parasitic inductance (ESL: under several tens pH) through a short interconnections between the on-chip PDN and decoupling capacitors as well as the largest capacitance (up to several uF) by stacking the additional decoupling capacitors to 3D-IC systems.

Multi-helix inductor of wireless power transfer system for 3-D stacked package

In this paper, the performance of package-level wireless power transfer (WPT) is compared and with respect to Z21 and voltage transfer ratio (VTR). The Z21 (transfer impedance) of three different types of inductors is analyzed and the transferred voltage is measured by applying a signal corresponding to a parallel-resonant frequency. The size of these inductors is implemented within 8 mm × 8 mm in which the parallel resonance is designed with a frequency band of 100 MHz ~300 MHz. When applying a sinusoidal signal generated from a signal generator, the proposed multi-helix inductor shows a VTR efficiency of 56.25 %. The proposed structure of the multi-helix inductor represents the most excellent VTR performance and is the most proper configuration of a package-level WPT system.

TSV-based decoupling capacitor schemes in 3D-IC

In this study, the scheme of a TSV-based decoupling capacitor stacked chip (DCSC) is proposed as a decoupling capacitor scheme to be possibly implemented in 3D-IC. The conventional decoupling capacitor schemes to be applied in a 3D-IC system include on-chip NMOS capacitors and package-level decoupling capacitor solutions. The proposed TSV-based DCSC scheme that can improve a disadvantage (i.e., relatively small capacitances) in the conventional on-chip NMOS capacitors and a limitation in package-level decoupling capacitor solutions represents excellent 3D-PDN (power delivery network) performance. In the comparison of the proposed TSV-based DCSC scheme with the conventional decoupling capacitor schemes, the propose scheme shows a similar level to the chip PDN that implements on-chip NMOS capacitors more than 10 nF and an SSN suppression effect of 93% compared to that of on-package decoupling capacitors. However, in the case of the on-chip NMOS capacitors, as an additional chip area, few mm × few mm, is required to ensure a capacitance of 10 nF, it is a scheme that has a limitation in increasing chip sizes. In conclusion, the proposed TSV-based DCSC is a decoupling capacitor solution that represents the most appropriate and excellent PDN performance in a 3D-IC system.

PDN analysis of TSV based decoupling capacitor stacked chip (DCSC) in 3D-ICs

In this paper, we introduce a new decoupling capacitor stacked chip (DCSC) with discrete capacitors and through-silicon-vias (TSVs) that can be implemented into a multi-stacked 3D-IC system. The core idea of the proposed TSV-based DCSC is stacking the decoupling capacitors such as a silicon-based NMOS capacitor and a discrete capacitor on the backside of a chip and connecting the capacitors to the chip-power distribution network (PDN) through TSVs. A new TSV based DCSC structure that has the advantages of chip-level NMOS capacitor (under several tens pH) and package-level decoupling capacitor (up to several uF) solutions, which represent the conventional decoupling capacitor solution, is proposed. The proposed DCSC is a proper structure for implementing into multi-stacked 3D-IC systems through using the TSV technology. In addition, 3D PDN impedance variations are analyzed according to the number of TSVs in a multi-stacked 3D-IC system that is applied to DCSC and its arrangement. It is possible to achieve a robust 3D PDN for the power noise by using a TSV based DCSC and by arranging power as many TSVs as possible uniformly.

Reductions in power noise and system area burden using wireless power transfer scheme in 3D package

Design challenges in 3D packages, which represent a system bandwidth of Tera Byte/sec, include serious SSN and large system area burden. For overcoming such design challenges, a package-level WPT scheme is proposed. Also, a proper inductor structure for 3D packages is proposed and verified through measuring the power efficiency of the WPT scheme according to inductor types. The WPT scheme in 3D packages that uses magnetic field resonance shows a noise filtering characteristic that significantly reduces power noise. In addition, the WPT system can reduce system area burden, as we can get rid of power interconnections, such as power balls and power TSVs, in 3D package/ICs based on its WPT scheme.

TSV Decoupling Schemes

Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.

Wireless power distribution network for 3D package using magnetic field resonance

In this paper, a wireless power transfer (WPT) scheme using magnetic field resonances for 3D packages is proposed and a wireless power distribution network (PDN) in a WPT system is analyzed in terms of the simultaneous switching noise (SSN). For analyzing the wireless PDN impedance characteristic and the power efficiency, a ball grid array (BGA) package with a size of 35 mm×35 mm is fabricated. Also, a new schematic of the wire PDN is defined to analyze a WPT system applied to the WPT system in terms of SSN. The impedance (Z11) characteristics between the interconnection-based hierarchical PDN structure and the hierarchical PDN based on the proposed WPT scheme are compared and analyzed. The package-level WPT system proposed in this study represents excellent wireless PDN impedance characteristics in decreasing the power noise occurred in a 3D package.