Kyoungchoul Koo

Analytical expressions for maximum transferred power in wireless power transfer systems

In this paper, we present the analytical expressions of the resonant peaks of input impedance and the frequencies of maximum transferred power in the wireless power transfer systems in case of tight magnetic coupling. The analytical expressions predict the frequencies of power source where the maximum power is transferred in both cases of the constant AC voltage source and the constant AC current source. We prove that the resonant frequencies of the input impedance in the wireless power transfer systems coincide with the frequencies at which the transferred power is maximized for the constant AC voltage source and the constant AC current source. The test vehicles of the coupled rectangular coils are simulated with 3D EM solver and fabricated on printed circuit boards. Experimentally, it is verified that the analytical expressions predict the changes in the resonant peaks of input impedance of the wireless power transfer systems, its relationship with frequencies of maximum transferred power and their dependency with the source type in the wireless power transfer systems.

Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects

In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN.

A Compact and Wideband Electromagnetic Bandgap Structure Using a Defected Ground Structure for Power/Ground Noise Suppression in Multilayer Packages and PCBs

In this paper, we propose a compact and wideband electromagnetic bandgap (EBG) structure using a defected ground structure (DGS) to significantly enhance the wideband suppression of power/ground noise coupling in multilayer packages and printed circuit boards. The proposed EBG structure is implemented simply by adding a rectangular-shaped DGS which is etched periodically onto the ground plane without changing any other geometrical parameter from a mushroom-type EBG structure. The DGS effects on the fL and fU are thoroughly analyzed using the dispersion characteristics. We experimentally verified that the proposed EBG structure achieved the wideband power/ground noise suppression (below -40 dB) between 2.5 and 16.2 GHz. In addition, we demonstrated the considerable reduction in fL from 3.4 to 2.5 GHz and a significant increase in fU from 9.1 to 16.2 GHz when compared with the mushroom-type EBG structure.

Modeling of Eye-Diagram Distortion and Data-Dependent Jitter in Meander Delay Lines on High-Speed Printed Circuit Boards (PCBs) Based on a Time-Domain Even-Mode and Odd-Mode Analysis

Crosstalk induced in a meander delay line produces a significant amount of waveform distortion and data-dependent jitter at the output port. This paper introduces an interpretation of the eye-diagram distortion and the jitter generation mechanism based on a time-domain even- and odd-mode analysis of a coupled transmission line structure. From the proposed analysis, this paper proposes jitter-estimation equations for both the short and long unit line delay cases. The eye-diagram distortion and timing jitter are predicted and estimated, respectively. In order to verify the jitter-estimation equations, a series of microstrip-type printed circuit board test vehicles with the meander delay line are fabricated and tested. The measured jitter shows good agreement with the proposed jitter-estimation equations.

Impact of PCB design on switching noise and EMI of synchronous DC-DC buck converter

Synchronous DC-DC buck converters operate under a few MHz but generate broadband noise up to GHz range due to its switching operation. The noise causes EMI problem through radiation and switching noise at the converter output from direct conduction. To control EMI and switching noise at the converter output, proper PCB design plays a critical role. This paper evaluates three types of GND plane layout and three types of high-voltage AC node layout for synchronous DC-DC buck converter test benches with 4-layer stack-up PCB. Transverse electromagnetic (TEM) cell measurement and time-domain measurement of switching noise at the converters output were performed for the evaluation. The source of EMI, switching noise and magnitude difference over layouts were analyzed by the impedance measurement on the test benches.

Modeling and Measurement of Power Supply Noise Effects on an Analog-to-Digital Converter Based on a Chip-PCB Hierarchical Power Distribution Network Analysis

In this paper, a model of power supply noise (PSN) effects on an analog-to-digital converter (ADC) in a hierarchical structure is proposed. The ADC performance is determined by not only on-chip characteristics but also off-chip characteristics. Therefore, chip-package-printed circuit board (PCB) coanalysis and comodeling are required to accurately evaluate the performance of the ADC. We propose the comodel which allows the estimation and analysis of PSN effects on the ADC including off-chip characteristic. The proposed model includes three separate submodels: a power distribution network (PDN) model from the power/ground of the PSN source to the ADC power/ground, an on-chip circuit model from the ADC power/ground to the ADC inputs, and an ADC behavioral model from the ADC inputs to the factor of the effective number of bits (ENOB), which is one of the ADC performance factors. By applying a segmentation method for the PDN model, an analytical model for the on-chip circuit model, and a MATLAB model for the ADC behavioral model, fast, precise, and broadband estimations of the PSN effects are achieved. To validate the proposed models, an ADC was fabricated by a 0.13-μm CMOS process and wire bonded to the designed PCB. The ENOB of the ADC was measured by sweeping the PSNs frequency from 1 MHz up to 3 GHz, which was injected into the PCB to discover which noise frequency is critical to an ADC designed with a chip-PCB hierarchical structure. The results estimated by the proposed model correlated well with the cosimulated and measured results. The proposed modeling procedure saves the chip, package, and PCB designers time and computation resources to achieve high-quality analog devices or mixed-mode systems and provides an intuitive understanding of the noise effect.

Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs

In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth limitation of the conventional decoupling capacitor solutions in three-dimensional-integrated circuits (3-D-ICs), as exhibited by expensive on-chip metal-oxide-semiconductor (MOS) decoupling capacitors and inductive off-chip discrete decoupling capacitors. In particular, in comparison to the on-chip decoupling solutions, such as MOS, metal-insulator-metal and deep trench capacitors, the proposed TSV-based DCSC represents several advantages, such as small leakage currents, large capacitances ranging from tens of nF to a few μF, low equivalent series inductance (ESL) with tens of pH, and high flexibility in TSV arrangements. The proposed TSV-based DCSC can be applied by mounting decoupling capacitors, such as Si-based MOS capacitors and discrete capacitors, on the backside of a chip and connecting the capacitors to the on-chip power delivery network (PDN) through TSVs. To demonstrate the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) of the TSV-based DCSC with those of the well-known conventional decoupling capacitor methods. The TSV-based DCSC was found to exhibit the advantages of both low on-chip level ESL (under several tens of pH) and high off-chip level capacitance (up to several μF). Additionally, the PDN impedance properties of the TSV-based DCSC were analyzed with respect to the variations in the number of power/ground TSV pairs, on-chip PDN size, and capacitance values of the stacked off-chip discrete decoupling capacitors using the segmentation method.

An On-Chip Electromagnetic Bandgap Structure using an On-Chip Inductor and a MOS Capacitor

An on-chip electromagnetic bandgap (EBG) structure using a CMOS process is proposed. The proposed structure is the first EBG structure devised to suppress simultaneous switching noise coupling in an on-chip power distribution network (PDN). The on-chip EBG structure utilizes an on-chip inductor and a MOS capacitor to generate a stopband with a range of several GHz in an extremely small size; thus, the EBG structure can be embedded in on-chip PDNs. The proposed on-chip EBG structure was fabricated using a MagnaChip 0.18 μm CMOS process, and we successfully verified a 9.24 GHz stopband, from 1.26 to 10.5 GHz, with an isolation level of 50 dB.

Modeling and Analysis of Power Supply Noise Imbalance on Ultra High Frequency Differential Low Noise Amplifiers in a System-in-Package

In this paper, we analyze the power supply noise imbalance and its effects on simultaneous switching noise coupling to an ultra high frequency differential low noise amplifier (LNA) in a system-in-package (SiP) through an off-chip power distribution network (PDN). On and off-chip sources of power supply noise imbalance in a LNA in a SiP were analyzed. A simultaneous switching noise coupling coefficient for the differential LNA output caused by power supply noise imbalance was simulated through co-modeling a hierarchical on and off-chip PDN. The simulation results were validated by measuring the simultaneous switching noise coupling voltage at the differential LNA output. Further validation of four types of a LNA with different PDN designs demonstrates that simultaneous switching noise coupling to the differential LNA output caused by power supply noise imbalance highly depends on the design of the PDN of the SiP.

Vertical Noise Coupling From On-Chip Switching-Mode Power Supply in a Mixed-Signal Stacked 3-D-IC

In this paper, we propose a fast and accurate model of the vertical noise coupling from an on-chip switching-mode power supply (SMPS) to a low noise amplifier (LNA) in a stacked 3-D-IC. To achieve both speed and accuracy, the model is based on the analytic formulas of static R, L, and C parasitic extraction, and includes consideration of the phase difference in the on-chip inductors using a new iterative calculation method. The proposed model and the prediction of vertically coupled noise at the LNA output using the model are experimentally validated on a fabricated stacked 3-D-IC consisting of an onchip SMPS and LNA. Good agreement with the measurements is confirmed in both the frequency domain and the time domain. The enhancements of the proposed model, including the broad model bandwidth (<; 4 GHz) as good as 3-D EM solver and 99% reduction of the simulation elapsed time (2 s) from 3-D EM solver, are confirmed. This paper also analyzes: 1) the impact of vertical noise coupling on the RF signal gain performance of the LNA and 2) the impact of variation in the stacking configuration, location, and thickness of the stacked LNA on the vertical noise coupling using the proposed model. Based on the results of our analysis, this paper proposes and verifies an effective method to reduce the vertical noise coupling using the proposed model.