Jun So Pak

High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic RLGC equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation

In this paper, we show the electrical characteristics of TSV (through silicon via) depending on structural parameters such as TSV pitch, TSV height, TSV size and thickness of SiO2 for DC leakage blocking between TSV and silicon substrate, and material parameter of silicon substrate such as silicon resistivity in case of single silicon substrate. And we also show X-talk characteristics of two TSVs depending on distance of two signal TSVs and different locations of two signal TSVs and two ground TSVs in array type arrangement of TSV. Additionally, we show the electrical characteristics of TSV depending on number of stacked TSVs. All electrical characterizations on this paper are obtained using commercial 3-D full wave simulator and spice type circuit simulator such as HFSS of Ansoft Corporation and ADS of Agilent Corporation, respectively.

PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models

The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and analyzed using a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz. The proposed modeling and analysis methods for the P/G TSV and chip-PDN are fundamental for estimating the PDN impedances of 3D TSV ICs because they are composed of several chip-PDNs and several thousands of P/G TSV connections. Using the proposed P/G TSV array model, we obtained very efficient analyses and estimations of 3D TSV IC PDNs, including the effects of TSV inductance and multiple-TSV inductance, depending on P/G TSV arrangement and the number of stacked chip-PDNs of a 3D TSV IC PDN. Inductances related to TSVs, combined with chip-PDN inductance and capacitance, created high upper peaks of PDN impedance, near 1 GHz. Additionally, the P/G TSV array produced various TSV array inductance effects on stacked chip-PDN impedance, according to their arrangement, and induced high PDN impedance, over 10 GHz.

Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach

Active circuit to through silicon via (TSV) noise coupling

In this paper, we propose a coupling model between through silicon via (TSV) and substrate based on a 3-Dimensional transmission line matrix (3D-TLM), which utilizes equivalent lumped circuit model of silicon substrate and TSV. The proposed model is verified by S-parameter simulations using a 3D field solver and analyzed with various structural parameters: TSV diameter, distance between TSV and noise source, and silicon substrate height. Based on the model, timing jitter degradation on phase locked loop (PLL) caused by substrate noise coupling is investigated. A shielding technique using a guard ring structure is applied to suppress the coupling noise.

Slow wave and dielectric quasi-TEM modes of Metal-Insulator-Semiconductor (MIS) structure Through Silicon Via (TSV) in signal propagation and power delivery in 3D chip package

The effects of slow wave and dielectric quasi-TEM modes due to MIS (Metal-Insulator-Semiconductor) structure TSV (Through-Silicon-Via) are analyzed by using the proposed MIS TSV model and the measured results. Since MIS TSV has larger surface, longer length, and smaller insulator thickness than those of conventional on-chip metal lines, the stronger effects of slow wave and dielectric quasi-TEM modes of MIS structure on electrical performance appear. After obtaining the MIS structure TSV model with the dimension variables based on the measurement and 3D full wave simulation, two slow wave and dielectric quasi-TEM modes effects on MIS TSV electrical characteristics are analyzed in the aspects of signal propagation and power delivery.

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structures impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.

High-Frequency Scalable Modeling and Analysis of a Differential Signal Through-Silicon Via

An analytic scalable model of a differential signal through-silicon via (TSV) is proposed. This TSV is a ground-signal-signal-ground (GSSG)-type differential signal TSV. Each proposed analytical equation in the model is a function of the structural and material design parameters of the TSV and the bump, which is scalable. The proposed model is successfully validated with measurements up to 20 GHz for the fabricated test vehicles. Additionally, the scalability of the proposed model is verified with simulations by using Ansoft HFSS to vary the design parameters, such as the TSV diameter, pitch between TSVs, and TSV oxide thickness. On the basis of the proposed scalable model, the electrical behaviors of the GSSG-type differential signal TSV are analyzed with respect to the design variations in the frequency domain. Additionally, the electrical performances of a GSSG-type differential signal TSV are evaluated and compared to that of a ground-signal-ground-type single-ended signal TSV, such as insertion loss, characteristic impedance, voltage/timing margin, and noise immunity.

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs

It is widely-known that coupling exists between adjacent through-silicon vias (TSVs) in 3D ICs. Since this TSV-to-TSV coupling is not negligible, it is highly likely that TSV-to-TSV coupling affects crosstalk significantly. Although a few works have already analyzed coupling in 3D ICs, they used S-parameter-based methods under the assumption that all ports in their simulation structures are under 50-Ω termination condition. However, this 50-Ω termination condition does not occur at ports (pins) of gates inside a 3D IC. In this paper, therefore, we analyze TSV-to-TSV coupling in 3D ICs based on a lumped circuit model with a realistic high-impedance termination condition. We also analyze how channel affect TSV-to-TSV coupling differently in different frequency ranges. Based on our results, we propose a technique to reduce TSV-to-TSV coupling in 3D ICs.