Evan E. Davidson

Package Electrical Design

Chip wires are used to form on-chip circuits and their interconnections, whereas package wires are used to interconnect the chips. The interface circuit for an incoming signal is commonly referred to as a receiver, whereas the interface circuit for an outgoing signal is referred to as a driver. A complete description of the terminal properties of these circuits and how they interact with the electrical package design is discussed in this chapter, along with the design guides to ensure reliable and predictable performance.

Electrical Design of a High Speed Computer Packaging System

A methodology for optimizing the design of an electrical packaging system for a high speed computer is described The pertinent parameters are first defined and their sensitivities are derived so that the proper design trade-offs can ultimately be made. From this procedure, a set of rules is generated for driving a computer-aided design (CAD) system. Finally there is a discussion of design optimization and circuit and package effects on machine performance.

The design of the ES/9000 module

The ES/9000 thermal conduction module (TCM) is a significant improvement over the TCMs used in the current IBM 3090 series of mainframes. Included in the features of this module, which supports an order of magnitude increase in usable circuits, are a glass ceramic substrate material, buried engineering change wires, partial thin film redistribution, and on-module decoupling capacitors. The physical attributes and the electrical design considerations are described. The result is a packaged electronic technology that supports a machine cycle time that is approximately two times faster than the original 3090 technology. >

SoC or SoP? A balanced approach!

System-on-a-Chip (SoC) is being touted by the semiconductor industry as a means for incorporating all of the important electronic functions required for a product onto a single die. The rest of the system unit would consist of cheap pedestrian parts from other vendors. The beauty of this well hyped concept is that all the value-add and revenue would go to the semiconductor companies while other technology providers will be left with low margin scraps. In some cases, this assertion from the semiconductor companies will be correct. On the other hand, there will be cases where SoC will not be the best business case because of excessively complex process requirements and oversized low yielding chips. For these cases, partitioning the SoC functions and placing them onto small few-chip-modules (FCMs) can result in a lower system cost with no performance sacrifice. It is the goal of this paper to justify this premise.

The design of ES/9000 module

The technology enhancements appearing in the glass ceramic TCM (thermal conduction module) of the ES/9000 systems are described and related to the system performance requirements. This module is larger, holds more circuits, supports higher power chips, and has more and faster signal connections than any of its predecessors. To assure the operational integrity of this module, much attention was paid to its electrical design. The interconnection and noise rules were carefully generated through extensive modeling and circuit simulation. Sophisticated design tools were generated to keep track of the noise and estimate the delay on each and every path in the TCM. A comprehensive set of measurements on specially built test vehicles measured in specialized testers was used to confirm the accuracy of the modules and rules. As a result, the TCM can support more functions and faster cycle times at a better quality level.<<ETX>>

Large chip vs. MCM for a high-performance system

The capabilities of modern semiconductor processes enable us to design a system on a chip. This implies a large function on a large chip. However, as we approach-and eventually exceed-a 1-GHz clock rate, it is valid to ask whether partitioning this chip into a few smaller chips and using a multichip module (MCM) to interconnect the functions is better for performance and cost. This article explores the design, performance, and cost issues for a large chip and an MCM, focusing primarily on the on-chip and off-chip delays and the trade-offs between the two. It also shows performance trends for each approach, to help us understand future performance limits for microprocessors.

The performance choice: a study of chip and package densities

A large circuit partition has been packaged using both single-chip modules (SCM) and multichip modules (MCM). It is shown that the use of closely packed chips on an MCM can readily offset the perceived advantages of large chips with high circuit counts when they are coarsely packed using SCMs on a printed circuit board (PCB). it is demonstrated that, since circuit accessibility monotonically increases with chip capacity and MCM is always better than SCM, the best packaged electronics technology would be made up of largest possible chip capacities on an MCM package. The only caution is that the chip size should not get so large that the MCM chip packing density suffers too much. Also, it is important that the MCM and chip site count be large enough to allow all the cycle time setting paths to be placed on one MCM for this analysis to be valid.<<ETX>>

Long lossy lines (L/sup 3/) and their impact upon large chip performance

The semiconductor industry expects the performance of microprocessors to continue at its current rate of improvement, i.e. clock rates should double every two to three years. This is a commendable goal, but it is also fair to question whether this is an achievable goal. The fundamental problem is that as ground rules are reduced, the natural tendency is to make smaller conductor cross-sectional areas. The result is a high resistance line that exhibits slow wave propagation effects (Ho et al, 1982). This reduces the general performance expectations. As circuits become faster and denser on the chip, line delays become greater than expected. This problem is analyzed and potential chip and packaging solutions are offered. Clock rate predictions for various design and process options are made. A tactical recommendation to consider a total packaged electronics solution is presented.

Multi-Chip Carriers in a System-on-a Chip-World

One of the key applications for foldable flex is to enable the use of 3-D (3Dimensional) MCMs (Multi-Chip Modules). This embodiment of a 3-D electronic package (E-package) represents the ultimate in packing density and it should be used whenever it benefits the application. The use of any MCM, however, brings up the issue of SoC (System-on-a-Chip) versus SiP (System-ina-Package). By its very nature, an MCM implies that the entire system is not on a single chip. Is eliminating all instances of an MCM what the SoC advocates mean when they so cavalierly bandy about the SoC acronym or can many SoCs exist on an MCM? Is the latter what the E-packaging community calls an SiP or is an SiP a more numerous collection of sub-SoCs (i.e., chips that are not SoCs) and/or SoCs on many single chip modules (SCMs) or one or more MCMs? These questions are very confusing and these questions are what will be explored in this chapter.

Area-array Design Principles

The advancement in silicon device technology with its associated frequency increases is having a major affects across all electronic market segments. These range from basic consumer electronics to high-performance computer and communications systems. As semiconductor ground rules and densities continue to improve, the resulting smaller chips are enabling more and more function to be integrated on an individual die; thus, enabling even smaller and lower cost chips than exist today. These relatively inexpensive parts are finding their way into affordable electronic products such as personal computers, cellular telephones, and palmtop computers.