George A. Katopis

When are transmission-line effects important for on-chip interconnections

Short, medium and long on-chip interconnections having line widths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

Decoupling capacitor effects on switching noise

The experimental procedures and test vehicles used for the characterization of the decoupling capacitor efficiency in reducing the power supply differential switching noise of the multichip-module (MCM) package structure employed in the IBM ES/9000 system are described. The experimental results are summarized for various switching elements. It is demonstrated that careful design of the test vehicles, tester systems, and probes makes the accurate measurement of Delta-1 noise feasible. Experimental results on the BOBCAT tester show that the decoupling capacitor efficiency in reducing the peak of the differential Delta-1 noise is 50-67%. This efficiency can be increased by reducing the effective inductance in the decoupling capacitor current return path. >

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBMs CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Extraction of /spl epsiv//sub r/(f) and tan/spl delta/(f) for printed circuit board insulators up to 30 GHz using the short-pulse propagation technique

In this paper, the self-consistent, frequency-dependent dielectric constant epsivr(f) and dielectric loss tandelta(f) of several materials are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. The simple measurement technique is performed in the time domain on representative printed circuit board wiring. Broadband, fully causal transmission-line models based on these results are generated up to 50 GHz for card wiring using low loss materials including BT, Nelco N4000-13, and Nelco N4000-13SI. Simulation and modeling results highlight the need for the accurate frequency-dependent dielectric loss extraction. Signal propagation based on these results shows very good agreement with measured step and pulse time-domain excitations and provides validation of the measurement and model generation technique

The importance of inductance and inductive coupling for on-chip wiring

The importance of inductance and inductive coupling for accurate delay and crosstalk prediction in on-chip interconnections is investigated experimentally for the top three layers in a five-layer wiring structure and guidelines are formulated. In-plane and between-plane crosstalk and delay dependence on driver and receiver circuit device sizes and line lengths and width are analyzed with representative CMOS circuits. Simplified constant-parameter, distributed coupled-line RLC-circuit representation that approximates the waveforms predicted with frequency-dependent line parameters is shown to be feasible.

Package Electrical Design

Chip wires are used to form on-chip circuits and their interconnections, whereas package wires are used to interconnect the chips. The interface circuit for an incoming signal is commonly referred to as a receiver, whereas the interface circuit for an outgoing signal is referred to as a driver. A complete description of the terminal properties of these circuits and how they interact with the electrical package design is discussed in this chapter, along with the design guides to ensure reliable and predictable performance.

MCM technology and design for the S/390 G5 system

The multichip module (MCM) that contains the central electronic complex (CEC) of the S/390 G5 system is described in this paper. The glass-ceramic module, topped with six layers of polyimide full-field thin-film wiring for chipto-chip interconnection, represents IBM’s most advanced packaging technology. This MCM provides a large wiring capacity, with 595 meters of routed interconnection; it supports the highest synchronous interconnection performance in the industry at 300 MHz; and it allows for cooling flexibility at the system level—either a heat sink for air-cooled systems or a cooling “hat” for systems using refrigeration cooling. The physical and electrical characteristics of this packaging technology, necessary to support the aggressive system performance goals (1040 MIPS) of the IBM G5 Enterprise Servers, are presented here. In addition, the approach used to produce a robust electrical and physical design is described.

The design of the ES/9000 module

The ES/9000 thermal conduction module (TCM) is a significant improvement over the TCMs used in the current IBM 3090 series of mainframes. Included in the features of this module, which supports an order of magnitude increase in usable circuits, are a glass ceramic substrate material, buried engineering change wires, partial thin film redistribution, and on-module decoupling capacitors. The physical attributes and the electrical design considerations are described. The result is a packaged electronic technology that supports a machine cycle time that is approximately two times faster than the original 3090 technology. >

Mid-frequency simultaneous switching noise in computer systems

CMOS microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity from clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50 to 200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBMs CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm MCM on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

MCM-C/D design for the CMOS implementation of the S/390 system

The new Enterprise model for the S/390 system achieves an off chip bus speed of 167 MHz using as a first level package on an alumina based multichip substrate (MCM) with thin film redistribution. A description of the physical attributes of this substrate will be presented in this paper. The electrical considerations used for the design of this MCM are described with emphasis on the techniques used for the noise containment.