Barry J. Rubin

When are transmission-line effects important for on-chip interconnections?

Short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses, and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

Radiation and scattering from structures involving finite-size dielectric regions

A full-wave approach is presented for calculating the scattered fields produced by structures that involve finite-size dielectric regions. The dielectric is first approximated by an array of interlocking thin-wall sections; the electric field boundary conditions are then applied through the use of appropriate surface impedances. Rooftop basis functions, chosen to represent the surface current, are appropriately placed on the thin-wall sections in such a way as to accurately represent the polarization current while preventing fictitious charge within the dielectric. Rooftop currents are also used to represent the current on any conductor that may be present. The matrix elements are calculated, depending upon the distance between the source and field locations, through a scheme that employs Taylor series expansions and point source approximations. The technique is applied to scattering from dielectric cubes and composite dielectric-conductor structures, and to radiation from microstrip structures. Numerical convergence and agreement with the literature are demonstrated. >

When are transmission-line effects important for on-chip interconnections

Short, medium and long on-chip interconnections having line widths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive coupling for short lines, inductive coupling for medium-length lines, inductance and resistance of the current return path in the power buses and line resistive losses for the global wiring. Design guidelines and technology changes are proposed to achieve minimum delay and contain crosstalk for local and global wiring. Conditional expressions are given to determine when transmission-line effects are important for accurate delay and crosstalk prediction.

Reflection from a periodically perforated plane using a subsectional current approximation

The scattering from a zero thickness plane having finite sheet resistance and perforated periodically with apertures is calculated for arbitrary plane wave illumination. The surface current density within the unit cell is approximated by a finite number of current elements having rooftop spatial dependence. The transverse electric field is expressed in terms of the current, and the electric field boundary condition is satisfied in an integral sense over the conductor, generating a finite dimension matrix equation whose solution is the current density. Since the conductor shape is defined through the locations of subsectional current elements, arbitrary shaped apertures can be handled. The reflection coefficient and current distribution are calculated for square apertures in both perfectly conducting and resistive sheets, and for cross-shaped apertures. Finite resistivity is shown to cause the magnitude of the transverse magnetic (TM) reflection coefficient to decrease more rapidly and its phase to decrease less rapidly, as the angle of incidence approaches glancing. Through detailed plots of the current density, the current crowding around the apertures is made clearly evident.

Extraction of /spl epsiv//sub r/(f) and tan/spl delta/(f) for printed circuit board insulators up to 30 GHz using the short-pulse propagation technique

In this paper, the self-consistent, frequency-dependent dielectric constant epsivr(f) and dielectric loss tandelta(f) of several materials are determined over the range 2 to 30 GHz using a short-pulse propagation technique and an iterative extraction based on a rational function expansion. The simple measurement technique is performed in the time domain on representative printed circuit board wiring. Broadband, fully causal transmission-line models based on these results are generated up to 50 GHz for card wiring using low loss materials including BT, Nelco N4000-13, and Nelco N4000-13SI. Simulation and modeling results highlight the need for the accurate frequency-dependent dielectric loss extraction. Signal propagation based on these results shows very good agreement with measured step and pulse time-domain excitations and provides validation of the measurement and model generation technique

Study of meander line delay in circuit boards

A moment technique is used to determine the propagation delay in meander (serpentine) delay lines located in printed circuit boards of computer systems. The full three-dimensional effects of the meander structure including signal line thickness, right-angle bends, and skin-effect are included. A set of delay lines having different pitches are considered, and results are calculated and compared to those from two-dimensional simulations, other commercial codes, analytic formulas in the literature, and experimental measurements. Based on the consistency of the results and sensitivity analyses involving numerical gridding and frequency content, the delays calculated for meander lines situated in a homogeneous medium are accurate to better than a few tenths of a percent.

The importance of inductance and inductive coupling for on-chip wiring

The importance of inductance and inductive coupling for accurate delay and crosstalk prediction in on-chip interconnections is investigated experimentally for the top three layers in a five-layer wiring structure and guidelines are formulated. In-plane and between-plane crosstalk and delay dependence on driver and receiver circuit device sizes and line lengths and width are analyzed with representative CMOS circuits. Simplified constant-parameter, distributed coupled-line RLC-circuit representation that approximates the waveforms predicted with frequency-dependent line parameters is shown to be feasible.

Calculation of multi-port parameters of electronic packages using a general purpose electromagnetics code

A powerful code developed by the authors to solve radiation and scattering problems from arbitrary 3D dielectric-conductor structures is modified to provide the terminal characteristics of arbitrary package structures. By incorporating a general de-embedding procedure to eliminate end effects, Y- and S-parameters can be obtained for 3D transmission-line structures; other parameters such as the C and L matrices can also be obtained. Results for microstrip twin-tee and mesh-plane structures are presented and compared with results already in the literature.<<ETX>>

Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies

Accurate and fast estimation of VLSI interconnect thermal profiles has become critically important to estimate their impact on circuit/system performance and reliability, which is necessary for reducing product development time and achieving first-pass silicon success. Present commercial thermal analysis tools are incapable of simulating complex structures, particularly in the 3-D domain and are also difficult to integrate with existing design tools. Existing analytical thermal models are not perfect either: they are either not accurate enough or oversimplified. This paper uses a methodology, which exploits existing electrical resistance solvers for thermal simulation, to allow fast acquisition of thermal profiles of complex interconnect structures with good accuracy and reasonable computation cost. Moreover, for the first time, an accurate closed-form thermal model is developed. The model allows for an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace the detailed material information in non-critical regions so that complex interconnect structures can be simulated. Using these techniques, this paper demonstrates the simulation of a very complex interconnect structure (~9000 objects or 15 million meshed unknowns after first order isotropic equivalent medium replacement), which is a first time achievement in the area of interconnect thermal analysis. On the other hand, it is shown that an anisotropic equivalent medium is a much better approximation of real interconnect structures from the point of view of accuracy and computation.

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.