Evert Seevinck

Static-noise margin analysis of MOS SRAM cells

The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.

Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's

The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access. >

Generalized translinear circuit principle

It is shown that a generalized interpretation of the translinear (TL) principle leads quite naturally to an extension to MOS circuits. It is shown that two distinct classes of TL circuits exist, one suitable for bipolar and the other for MOS implementation. The MOS-translinear (MTL) circuit principle is derived and an initial classification of simple MTL circuits is proposed. Some examples are given of MTL circuits synthesizing nonlinear functions. >

An efficient low voltage, high frequency silicon CMOS light emitting device and electro-optical interface

A silicon light emitting device was designed and realized utilizing a standard 2-/spl mu/m industrial CMOS technology design and processing procedure. The device and its associated driving circuitry were integrated in a CMOS integrated circuit and can interface with a multimode optical fiber. The device delivers 8 nW of optical power (450-850 nm wavelength) per 20-/spl mu/m diameter of chip area at 4.0 V and 5 mA. The device emits light by means of a surface assisted Zener breakdown process that occurs laterally between concentrically arranged highly doped n/sup +/ rings and a p/sup +/ centroid, which are all coplanarly arranged with an optically transparent Si-SiO/sub 2/ interface. Theoretical and experimental determinations with capacitances and series resistances indicate that the device has an intrinsic high-frequency operating capability into the near gigahertz range.

A low-distortion output stage with improved stability for monolithic power amplifiers

A low-distortion class AB output stage with improved stability suitable for monolithic power amplifiers (P/sub 0/>or=40 W) is described. The concept has been verified on a 12-W breadboard version as well as on a partly integrated prototype, and is supported by computer simulations for P/sub 0/>or=40 W A biasing control law which guarantees predictable conduction of both output transistors at all times is implemented. This reduces crossover distortion and allows the customary quasi-p-n-p compound transistor to be eliminated, thus also improving stability. Linearity is improved by use of local negative feedback. Phase margin is improved by application of high-frequency feedforward. Measured phase margin is around 60 degrees and total harmonic distortion for a load of 7 Omega is about -80 dB at 20 kHz. >

MOS current gain cells with electronically variable gain and constant bandwidth

Two MOS current gain cells are proposed that provide linear amplification of currents supplied by several linear MOS V-I converters. The gain is electronically variable by a voltage or a current and can be made insensitive to temperature and IC processing. The gain cells have a constant (gain-independent) bandwidth. >

New techniques for high-frequency RMS-to-DC conversion based on a multifunctional V-to-I convertor

Two bipolar RMS-DC convertor circuits of the computing type which require no rectifier function are discussed. Improved frequency response is thus obtained. RMS-to-DC computation is carried out in the current domain. To make the circuit suitable for voltage driving, a dedicated V-to-I convertor is developed. Measured 1% bandwidths of the RMS-to-DC convertors are 35 and 22 MHz, respectively. Conversion error is less than 1% for the crest factors up to five. >

High speed current-mode signaling circuits for on-chip interconnects

As the technology scales, the global wire delay becomes a major bottleneck in realizing high performance SOCs. Apart from the technological efforts being made to overcome this problem, it is necessary to develop new circuit design techniques. This paper presents three current-mode circuits for high-speed signal propagation across long on-chip busses. Theoretical analysis has shown that a factor of three can be gained in propagation delay when current-mode (CM) signaling is used in comparison to voltage-mode (VM). In this paper, we show that the delay is reduced by more than a factor of 2 in current mode signaling by using the circuit techniques we propose in comparison to voltage-mode signaling in 0.13 /spl mu/m CMOS technology. This is without any significant power penalty. Further gains in speed are achieved at very high power consumption. The power dissipation on on-chip busses is a strong function of bus layout and data rate. We identified data rates for which the proposed current mode signaling circuits become more power efficient compared to voltage mode signaling circuits.

Offset cancelling circuit

An offset cancelling circuit to reduce the offset voltage at an integrated audio amplifier output is described. This offset voltage is detected using a low pass filter with a very large time constant. Only one small on-chip capacitor is needed. A value of 50 pF yields a - 3dB bandwidth of 5 Hz. The circuit was realized with a bipolar cell-based semicustom array.

Practical formulation of the relation between filter specifications and the requirements for integrator circuits

The design of integrated, high-frequency, continuous-time filters has made considerable progress in the past few years. As the signal frequencies increase the design of the integrator circuits used in most of these filters becomes more critical. To give direction to the circuit design, minimum specifications for the gain and phase of the integrator circuits would be helpful. A practical method for obtaining these integrator specifications from the filter specifications is developed. The method is applied to a sixth-order Chebyshev band-pass filter, and the result is verified by computer simulation. >