Evgueniy Stefanov

Thermal behavior of a superjunction MOSFET in a high-current conduction

In this paper, a detailed study of the superjunction MOSFET (SJ-MOSFET) thermal behavior on high-current conduction is presented. First, the heat-generation (HG) process and its dependence on device geometry and biasing conditions are elucidated from numerical-simulation tools. Later, the resultant temperature distribution is evaluated by simulation, thus, acquiring a physical understanding of its impact on the electrical characteristics and failure mechanisms, particularly at short-circuit operation. The obtained results show relevant differences with respect to the thermal behavior of conventional power MOSFETs. As a matter of fact, the maximum HG in SJ-MOSFET is found at a certain distance from the surface, which principally depends on the drift length. This fact has important implications on the device reliability prediction and a compact electrothermal modeling

Electrical and Physical Characterization of 150-200V FLYMOSFETs

A vertical n-channel 150V-200V FLYMOSFET is proposed in this work for the first time. Initially, spreading resistance profiling, scanning capacitance microscopy and process simulation are used to provide an accurate 1D and 2D device physical characterization. Concerning the electrical study, FLYMOSFET measurements show superior RonS-BVdss trade-off in comparison with the conventional power MOSFET and improved UIS ruggedness in front of the super junction MOSFET

Switching performance of 65V vertical N-channel FLYMOSFETs

In this paper, the switching performance of 65V vertical N-channel FLYMOSFETs is investigated for the first time and compared with a conventional vertical DMOSFET (VDMOSFET). It is shown that measurements of the different capacitances and the gate charge of the two devices are comparable. A 2D simulation study of two equivalent structures (i.e. FLYMOSFET and VDMOSFET exhibiting the same breakdown voltage) confirms that floating islands did not cause parasitic or new phenomenon, in the case of weakly doped islands.

Super-Junction PIN Photodiode to Integrate Optoelectronic Integrated Circuits in Standard Technologies: A Numerical Study

The use of super-junction (SJ) techniques in PIN photodiodes is proposed in this letter for the first time with the objective to assist the optoelectronic integrated circuits (OEICs) implementation in complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS) and bipolar-CMOS-double diffused MOS (BCD) technologies. Its technological viability is also discussed to make it credible as an alternative to other OEICs approaches. Numerical simulation of realistic SJ-PIN devices, widely used in high power electronics, demonstrates the possibility to integrate high-performance CMOS-based OEICs in epitaxial layers with doping concentrations above 1×1015 cm-3. The induced lateral depletion at low reverse biased voltage, assisted by the alternated N and P-doped pillars, allows high-speed transient response in SJ-PIN detecting wavelengths between 400 and 800 nm. Moreover, other important parameters as the responsivity and the dark current are not degraded in respect to the conventional PIN (C-PIN) structures.

Current sense dynamics during turn-on of power MOSFET

During power MOSFET turn-on transient abnormal over-/undershoot currents in the sense FET are measured, impacting dramatically the mirror precision. The objective of the work is, based on sense FET explored dynamics, to elaborate guidelines to specify validation time for the sense measurement during turn-on, which is crucial for the system performance to achieve reliable control. We report analysis of current sense dynamics during turn-on of trench-gated MOSFET/65V. 3D device model is developed to study the impact of threshold voltage shift between power and sense device on CSR and sensing error, where wide spectrum of PWM mode switching slew rates are simulated.

Self-heating analysis of power MOSFET module during burn-in test

The paper deals with the thermal behavior for paralleled MOSFETs module during accelerated cycling burn-in test in harsh ambient and current conditions. The aim of the work is to optimize the key parameters acting on the self-heating in order to avoid undesirable failures resulting from overheating. An electro-thermal model is developed to simulate the device temperature during the test. Well calibrated to the experimental data for Ron and avalanche phases, our model allowed realistic thermal prediction. The impact of gate bias, pulse time, as well as disparities of breakdown voltage between the FETs was analyzed and the test conditions were optimized.