Jean-Michel Reynes

Electrical and Physical Characterization of 150-200V FLYMOSFETs

A vertical n-channel 150V-200V FLYMOSFET is proposed in this work for the first time. Initially, spreading resistance profiling, scanning capacitance microscopy and process simulation are used to provide an accurate 1D and 2D device physical characterization. Concerning the electrical study, FLYMOSFET measurements show superior RonS-BVdss trade-off in comparison with the conventional power MOSFET and improved UIS ruggedness in front of the super junction MOSFET

Power MOSFET R DSon under repetitive avalanche cycling

In this paper, a low voltage vertical power MOSFET is submitted to repetitive avalanche cycles under very high current (≫400A) at high temperature (≫150°C). Electrical characteristics such as B<inf>VDSS</inf>, I<inf>GSS</inf>, I<inf>DSS</inf>, V<inf>F</inf>, V<inf>GSth</inf> and R<inf>DSon</inf> are systematically tested along cycling. After a large number of avalanche pulses well above products requirements measurements show that R<inf>DSon</inf> decreases with the number of avalanche cycles whereas other parameters stay constant. With a simple model of R<inf>DSon</inf> measurement and new measurements such as the resistance of the metallization between two bonding wires we can connect this unexpected drop of R<inf>DSon</inf> measurement to MOSFET source electrode evolution.

Switching performance of 65V vertical N-channel FLYMOSFETs

In this paper, the switching performance of 65V vertical N-channel FLYMOSFETs is investigated for the first time and compared with a conventional vertical DMOSFET (VDMOSFET). It is shown that measurements of the different capacitances and the gate charge of the two devices are comparable. A 2D simulation study of two equivalent structures (i.e. FLYMOSFET and VDMOSFET exhibiting the same breakdown voltage) confirms that floating islands did not cause parasitic or new phenomenon, in the case of weakly doped islands.

Temperature Sensing for Power MOSFETs in Short-Duration Avalanche Mode

The purpose of this paper is based on the estimation of power MOSFET junction temperature during a short-duration avalanche mode. Therefore, an experiment has been developed and results have been correlated with simple electrothermal modeling. The simple electrothermal model allows monitoring of junction temperature by simple measurements of the ID(t) and BVdss(t) waveforms. Accurate extraction of model parameters is linked with precise recording of the instantaneous avalanche voltage. Indeed, avalanche voltage is impacted by two phenomena, namely, the current-induced ohmic voltage drop and the shift of the breakdown voltage due to self-heating effects. This paper highlighted that during avalanche behavior, MOSFETs exhibit a dynamic avalanche resistance Rav, which is far in excess of their classical on-state resistance Rdson.

Interest of surface treatment at gate oxide level for power MOSFETs quality and reliability

In this paper, the impact of pre-gate and post-gate oxide surface treatments on the reliability and the robustness of low power vertical MOSFET dedicated to automotive applications are investigated. In these applications, components quality is linked with gate oxide robustness and tests like Qbd, TDDB and HTGB exist to evaluate its reliability. The study concludes that post-gate oxide cleaning has a significant impact on oxide quality as shown with Qbd on final product and GOI measurements. Moreover, an AFM characterization has demonstrated that a mechanical ultrasonic cleaning step can damage irreversibly gate oxide surface roughness in opposition to chemical surface treatment. Nevertheless, the TEM analysis of oxide-polysilicon interface does not highlight any difference. The root cause of power MOSFET failure mechanism is linked with gate oxide quality which depends to surface treatment performed. The cavitation erosion phenomenon has been highlighted to be responsible for Qbd degradation.

Estimation of power MOSFET junction temperature during avalanche mode: Experimental tests and modelling

Abstract In this paper, an experimental and numerical procedure has been developed to estimate the junction temperature of a power MOSFET when operating in avalanche mode of short duration. At first, a simplified electrothermal model proposed in literature has been recalled then we describe the experimental procedure that we have developed to extract the parameters necessary for its exploitation. The comparison between measurements and numerical simulation results of temperature and drain–source voltage shows that the proposed methodology leads to a quite accurate prediction of the MOSFET heating and drain–source voltage waveforms during avalanche mode.

Investigation of failure mechanisms in low-voltage power VDMOSFETs linked with gate oxide process quality

Devices dedicated to automotive applications have to reach exacting specifications especially in terms of reliability. The burn-in HTGB test is dedicated to evaluate gate oxide integrity with gate biased under high temperature. Therefore, gate oxide quality is an exacting parameter which contributes to device reliability. This paper is based on the study of planar technology and more precisely on vertical double-diffused power MOSFETs. First of all, the purpose of this work is to correlate the gate oxide process quality and the influence of wet cleanings at silicon level on die reliability. Actually, the cleaning performed just before oxide growth is linked with gate oxide robustness as shown with GOI measurements on dedicated structures and QBD measurements on power devices. Another key point is the homogeneity of breakdown voltage due to parallel MOSFETs used in application. Probe electrical results and TEM observations has demonstrated a correlation between BVdss establishment and cleaning used on silicon surface. In conclusion, the kind of cleaning performed at silicon level before oxide growth has been identified to generate irreversible damages for power VDMOSFETs.