Ewerson Carvalho

Dynamic Task Mapping for MPSoCs

Multiprocessor-system-on-a-chip (MPSoC) applications can consist of a varying number of simultaneous tasks and can change even after system design, enforcing a scenario that requires the use of dynamic task mapping. This article investigates dynamic task-mapping heuristics targeting reduction of network congestion in network-on-chip (NoC)-based MPSoCs. The proposed heuristics achieve up to 31% smaller channel load and up to 22% smaller packet latency than other heuristics.

Congestion-aware task mapping in heterogeneous MPSoCs

Multiprocessors systems-on-chip (MPSoCs) are a trend in VLSI design, since they minimize the design crisis represented by the gap between the silicon technology and the actual SoC design capacity. MPSoCs may employ NoCs to integrate several programmable processors, specialized memories, and other specific IPs in a scalable way. Besides communication infrastructure, another important issue in MPSoCs is task mapping. Dynamic task mapping is needed, since the number of tasks running in the MPSoC may exceed the available resources. Most works in literature present static mapping solutions, not appropriate for this scenario. This paper investigates the performance of mapping algorithms in NoC-based heterogeneous MPSoCs, targeting NoC congestion minimization. The use of the proposed congestion-aware heuristics reduces the NoC channel load, congestion, and packet latency.

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros

Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globally asynchronous, locally synchronous (GALS) design approaches should take over. The design of circuits using complex field programmable components like state of the art FPGAs follows this same trend. In GALS design, a critical step is the definition of asynchronous interfaces between synchronous regions. This paper proposes SCAFFI, a new asynchronous interface to interconnect modules inside FPGAs. The interface is based on clock stretching techniques to avoid metastability. Differently from other interfaces, it can use both logic levels for stretching and do not require the use of arbiters. Also, compactness of the implementation is enhanced by the use of dedicated FPGA hard macros. A GALS version implementation of an RSA cryptography core demonstrates the use of SCAFFI.

PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems

Dynamically and partially reconfigurable systems (DRS) are those where any portion of the hardware behavior can be altered at application execution time. These systems have the potential to provide hardware with flexibility similar to that of software, while leading to better performance and smaller system size. However, the widespread acceptance of DRSs depends on adequate support to design and implement them. This work proposes a framework for DRS design and implementation named PADReH. The approach is compared to other propositions available in the literature. The first steps of the framework implementation are described, involving methods and tools to control the hardware reconfiguration process and the generation of partial bitstreams. The main contribution of the work is to provide means to systematically reduce the lack of support currently hampering the adoption of DRSs as a mainstream technology.

Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs

Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a scenario that requires the use of dynamic task mapping. Static mappings have as main advantage the global view of the system, while dynamic mappings normally provide a local view, which considers only the neighborhood of the mapping task. This work aims to evaluate the pros and cons of static and dynamic mapping solutions. Due to the global system view, it is expected that static mapping algorithms achieve superior performance (w.r.t. latency, congestion, energy consumption). As dynamic scenarios are a trend in present MPSoC designs, the cost of dynamic mapping algorithms must be known, and directions to improve the quality of such algorithms should be provided without increasing execution time. This quantitative comparison between static and dynamic mapping algorithms is the main contribution of this work.

Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload

This work investigates the performance of different mapping algorithms in NoC-based MPSoCs with dynamic workload. The main cost function in mapping algorithms is to optimize the occupation of the NoC links. It is possible to achieve performance gains if the mapping algorithm is able to minimize NoC congestion.

Infrastructure for dynamic reconfigurable systems: choices and trade-offs

Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architectures might furnish enough performance for several classes of embedded systems. An associated advantage of these architectures is flexibility at the software level. In principle, hardware is not flexible. Thus, dedicated IP blocks must be inserted before chip design, or enough area can be reserved for them when using reconfigurable blocks. Dynamic self-reconfigurable systems (DSRSs) introduce flexibility to hardware. In DSRSs, IP blocks are loaded according to application demand, reducing area, power consumption and system cost. An MPSoC based platform, associated with dynamic reconfiguration, provides both hardware and software flexibility. This paper has two main goals. First, to present the necessary infrastructure for DSRSs, identifying which components are required in these systems, such as a configuration controller, configuration ports and reconfigurable IP interfaces. The second objective is to discuss practical implementations choices and area-performance tradeoffs. The paper employs case studies to access the advantages and problems related to different implementations for the communication infrastructure (bus and NoC), the configuration controller (hardware and software) and IP interfaces (LUT and tristate based).

Investigating runtime task mapping for NoC-based multiprocessor SoCs

Multiprocessor Systems on Chip (MPSoCs) are a trend in VLSI design, since they minimize the design crisis configured by the gap between the silicon technology and the actual SoC design capacity. An important issue in MPSoCs is task mapping. Applications running in MPSoCs execute a varying number of tasks simultaneously, where each task may be started at some distinct moment, according to applications requests. Thus, task mapping should be executed at runtime. This work investigates the performance of dynamic task mapping heuristics in NoC-base MPSoCs, targeting NoC congestion minimization. Tasks are mapped on demand, according to the NoC channels load. Results using congestion-aware mapping heuristics compared to a straightforwardly defined heuristic achieve better results. In average, it is possible to reach up to 31% smaller channel load, up to 22% smaller packet latency, and up to 88% less.

Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements Tools and a Case Study

Current technology allows building integrated circuits (ICs) complex enough to contain all major elements of a complete end product, which are accordingly called Systems-on-Chip (SoCs) [1]. A SoC usually contains one or more programmable processors, on-chip memory, peripheral devices, and specifically designed complex hardware modules. SoCs are most often implemented as a collection of reusable components named intellectual property cores (IP cores or cores). An IP core is a complex hardware module, created for reuse and that fulfills some specific task. Field Programmable Gate Arrays (FPGAs1) have revolutionized the digital systems business after their introduction, almost 20 years ago. The first FPGAs were fairly simple, being able to house a circuit with no more than a few thousand equivalent gates. They were launched in the mid eighties, at the same time when rather complex microprocessors like Intel 80386, Motorola 68020 and the first MIPS were already in the market or were about to be launched. Today, state-of-the-art FPGAs allow accommodating digital systems with more than 10 million equivalent gates in its reconfiguration fabric alone. Such devices can clearly be seen as a platform to implement SoCs. IP cores in such a platform may be implemented using the reconfigurable fabric or hard blocks, available all in the same device. In addition to the reconfigurable fabric, current FPGAs may contain one or a few microprocessors, up to hundreds of integer multipliers and memory blocks, and other specific modules.