Julian J. H. Pontes

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques

The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-established design practices. Examples are the use of multi-point communication architectures (e. g. busses) and designing fully synchronous systems. In addition, power dissipation is becoming one of the main design concerns due e. g. to the increasing use of mobile products. An alternative to overcome such problems is adopting Networks on Chip (NoCs) communication architectures supporting globally asynchronous locally synchronous (GALS) system design. This work proposes a GALS router with associated power control techniques, which enables low power SoC design. This is in contrast with previous works which centered attention in power reduction of SoC processing elements instead. The paper describes the asynchronous communication interface and the employed power control mechanism. The results obtained from simulation at the RTL level with timing show that, even when submitted to large rates of traffic injection, the proposed NoC displays a significant reduction in switching activity and consequently in power dissipation.

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros

Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globally asynchronous, locally synchronous (GALS) design approaches should take over. The design of circuits using complex field programmable components like state of the art FPGAs follows this same trend. In GALS design, a critical step is the definition of asynchronous interfaces between synchronous regions. This paper proposes SCAFFI, a new asynchronous interface to interconnect modules inside FPGAs. The interface is based on clock stretching techniques to avoid metastability. Differently from other interfaces, it can use both logic levels for stretching and do not require the use of arbiters. Also, compactness of the implementation is enhanced by the use of dedicated FPGA hard macros. A GALS version implementation of an RSA cryptography core demonstrates the use of SCAFFI.

A 65nm standard cell set and flow dedicated to automated asynchronous circuits design

This work proposes a new design flow for rapid creation and characterization of standard cell sets for asynchronous design. The flow is fully automated except for the cell layout generation step. It has been applied to the design of a standard cell set supporting the Teak asynchronous synthesis tool. Cells use a 65 nm gate length commercial CMOS process. An asynchronous RSA cryptography circuit provides the design flow validation.

Adapting a C-element design flow for low power

The interest in non-synchronous design of digital circuits is growing due to technology scaling into deep submicron transistor geometries and to the problems this scaling causes to keep synchronous design advantageous. To enable most non-synchronous styles, the C-element is a fundamental device that has to be available as logic primitive. A recently proposed design flow improved a standard cell library, adding to it a set of typical asynchronous cells. However, the original flow did not address low power cells explicitly, which is a requirement in many modern applications. This paper proposes the extension of the flow so that it can expand the cell set with low power components. To achieve this, the paper adds a new degree of freedom to cell design. The new standard cell set encompasses over 500 different C-element implementations. The cell set employs a 65nm commercial CMOS process and is fully compliant with the foundry standard cell library. A fully asynchronous RSA crypto core was designed with the new cells, producing savings of more than 35% in total power and more than 69% in leakage power.

Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects

In advanced CMOS technology, Single Event Effects due to high energy particle may cause different types of electrical effects when crossing silicon: from small delay variations, to bit flips, until permanent damage. Quasi Delay Insensitive asynchronous circuits are the most immune to delay variations thanks to the use of Delay Insensitive codes, but can be very sensitive to bit flips since a Single Event Effect may corrupt the handshake protocol. This paper presents a design technique to mitigate Single Event Effect by adding temporal redundancy to Delay Insensitive codes. This multiple bit fault tolerant design technique is adaptable to any 1-of-N DI code, and is particularly well suited to asynchronous Networks-on-Chip. The proposed Temporally Redundant Delay Insensitive codes have been evaluated using a Single Event Effect digital fault characterization environment. The result shows better SEE tolerance and reduced area and performance impact.

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing

This work presents the architecture and ASIC implementation of Hermes-AA, a flexible fully asynchronous network on chip router employing an adaptive routing algorithm. Hermes-AA enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specifically developed library of standard cell components. Area and timing characteristics for 65nm technology attest the quality of the design, which displays a maximum aggregated throughput of 7.75 Gbits/s

Hermes-a - an asynchronous NoC router with distributed routing

This work presents the architecture and ASIC implementation of Hermes-A, an asynchronous network on chip router. Hermes-A is coupled to a network interface that enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specific library of components. Area and timing characteristics for 180nm technology attest the quality of the design, which displays a maximum throughput of 3.6 Gbits/s.

An accurate single event effect digital design flow for reliable system level design

Similar to local variations and signal integrity problems, Single Event Effects (SEEs) are a new design concern for digital system design that arises in deep sub-micron technologies. In order to design reliable digital systems in such technologies, it is mandatory to precisely model and take into account SEEs. This paper proposes a new accurate design flow to model non-permanent SEE effects that can be applied at system level for reliable digital circuit design. Starting from low level SPICE-accurate simulations, SEEs are characterized, modeled and simulated in the digital design using commercial and well accepted standards and tools. The proposed design flow has been fully validated through a complete digital design, a cryptographic core implemented in a 32nm CMOS technology. Finally, using the SEE design flow, the paper presents some reliability impact analysis, both at standard cell level and design level.

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design

Classically, quasi-delay-insensitive asynchronous circuits based on weak-conditioned half-buffer employ the return-to-zero, 4-phase handshake protocol. This work scrutinizes the alternative return-to-one protocol and analyzes the effects of using it in practical circuits. A pipelined shift and add multiplier serves as case study. Return-to-one and return-to-zero versions of the circuit provide ground for extensive comparison. Experimental results point to reductions in static power and in forward propagation delay of up to 35% and 12%, respectively, when using return-to-one. Also, results indicate that mixing return-to-zero and return-to-one leads to dynamic power savings.

Two-phase protocol converters for 3D asynchronous 1-of-n data links

Design of fully synchronous System on Chip is becoming a challenging task. This task is even more difficult in advanced nodes and 3D designs, where the local and global variability can turns the timing closure an overwhelming task. In this way, the use of asynchronous circuits for long link and 3D link communication can provide better robustness to both local and inter-die variability and achieve faster timing closure by extending the Globally Asynchronous Locally Synchronous style to 3D architectures. However, while the four-phase protocol is well adapted for on chip Delay Insensitive communication, it cannot be adapted for off chip and 3D interface communication due to potential large interface delays. In this paper, we propose the use of two-phase Delay Insensitive Transition Signaling for 1-of-n codes as well as new four ↔ two-phase data converters. The proposed circuitry is able to reduce 20% the dynamic power and improve two times the four-phase throughput for long link communications.