Giulio Borghello

Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC

The Large Hadron Collider (LHC) running at CERN will soon be upgraded to increase its luminosity giving rise to radiations reaching the level of GigaRad Total Ionizing Dose (TID). This paper investigates the impact of such high radiation on transistors fabricated in a commercial 28 nm bulk CMOS process with the perspective of using it for the future silicon-based detectors. The DC electrical behavior of nMOSFETs is studied up to 1 Grad TID. All tested devices demonstrate to withstand that dose without any radiation-hard layout techniques. In spite of that, they experience a significant drain leakage current increase which may affect normal device operation. In addition, a moderate threshold voltage shift and subthreshold slope degradation is observed. These phenomena have been linked to radiation-induced effects like interface and switching oxide traps, together with parasitic side-wall transistors.

GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs

The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS technology in the forthcoming upgrade of the Large Hadron Collider at CERN. The total ionizing dose effects show limited influence in the drive current of all the tested nMOSFETs. Nonetheless, the leakage current increases significantly, affecting the normal device operation of the nMOSFETs. These phenomena can be linked to the charge trapping in the oxides and at the Si/oxide interfaces, related to both the gate oxide and the shallow trench isolation oxide. In addition, it has been observed that the radiation-induced effects are partly recovered by the long-term post-irradiation annealing. To quantify the total ionizing dose effects on DC characteristics, the threshold voltage, subthreshold swing, and drain induced barrier lowering have also been extracted for nMOSFETs.

Influence of LDD Spacers and H + Transport on the Total-Ionizing-Dose Response of 65-nm MOSFETs Irradiated to Ultrahigh Doses

The degradation induced by ultrahigh total ionizing dose in 65-nm MOS transistors is strongly gate-length dependent. The current drive decreases during irradiation, and the threshold voltage often shifts significantly during irradiation and/or high-temperature annealing, depending on transistor polarity, applied field, and irradiation/annealing temperature. Ionization in the spacer oxide and overlying silicon nitride layers above the lightly doped drain extensions leads to charge buildup as well as the ionization and/or release of hydrogen. Charge trapped in the spacer oxide or at its interface modifies the parasitic series resistance, reducing the drive current. The released hydrogen transports as H+ with an activation energy of ~0.92 eV. If the direction of the electric field is suitable, the H+ can reach the gate oxide interface and depassivate Si-H bonds, leading to threshold voltage shifts. Newly created interface traps are most prominent near the source or drain. The resulting transistor responses and defect-energy distributions often vary strongly in space and energy as a result, as demonstrated through current–voltage, charge-pumping, and low-frequency noise measurements.

Total ionizing dose effects on analog performance of 28 nm bulk MOSFETs

This paper uses the simplified charge-based EKV MOSFET model for studying the effects of total ionizing dose (TID) on analog parameters and figures-of-merit (FoMs) of 28nm bulk MOSFETs. These effects are demonstrated to be fully captured by the five key parameters of the simplified EKV model. The latter are extracted from the measured transfer characteristics at each TID. Despite the very few parameters, both the simplified large- and small-signal models present an excellent match with measurements at all levels of TID. The impacts of TID on essential parameters, including the drain leakage current, the threshold voltage, the slope factor, and the specific current, are then evaluated. Finally, TID effects on the transconductance Gm, the output conductance Gds, the intrinsic gain Gm/Gds and the transconductance efficiency Gm/Id are investigated.

Dose-Rate Sensitivity of 65-nm MOSFETs Exposed to Ultrahigh Doses

The radiation response of complementary metal–oxide–semiconductor (CMOS) gate oxides is typically insensitive to true dose-rate effects, but damage in deep-sub-micrometer technologies is dominated by ionization mechanisms in thick isolation oxides surrounding the transistors. Recent results in 65-nm FETs demonstrated that performance degradation in ultrahigh total ionizing dose (TID) experiments is due to defects in the isolation shallow trench isolation oxide or in the materials composing the lightly doped drain spacers. These insulators are thick, deposited, and crossed by a low electric field, characteristics similar to those typical of passivation oxides in linear bipolar technologies for which an enhanced low-dose-rate sensitivity (ELDRS) has been observed and systematically studied. We report in this paper the clear evidence of a dose-rate sensitivity of the TID-induced damage in both 130- and 65-nm CMOS technologies exposed to different radiation sources (X-rays and

Characterization of GigaRad Total Ionizing Dose and Annealing Effects on 28-nm Bulk MOSFETs

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Extending a 65nm CMOS process design kit for high total ionizing dose effects

-rays from a 60Co source). This sensitivity is attributed to mechanisms similar to those explaining ELDRS in bipolar devices and represents a significant challenge to the definition of a qualification procedure for circuits to be used in extreme radiation environments.