F. G. Ruiz

GA design of a thin-wire bow-tie antenna for GPR applications

A microgenetic algorithm has been applied to design a new ultrawideband thin-wire bow-tie antenna for ground-penetrating radar applications. The broadband performance of the antenna is achieved by resistive loading and by optimizing the number of wires and the angular distances between those wires. The radiation characteristics of the optimized antenna are discussed, and its performance is compared to that of a resistively loaded Wu-King dipole.

The Multivalley Effective Conduction Band-Edge Method for Monte Carlo Simulation of Nanoscale Structures

The trend toward continuous integration of the nanometer scale and the rise of nonconventional device concepts such as multigate transistors present important challenges for the semiconductor community. Simulation tools have to be adapted to this new scenario where classical approaches are not sufficiently accurate, and quantum effects have to be taken into account. This paper proposes a method of including quantum corrections in Monte Carlo (MC) simulations without solving the Schroumldinger equation. The approach, based on the effective conduction band-edge (ECBE) method, considers the effects of an arbitrary effective mass tensor, describing valley characteristics and confinement directions while avoiding the use of effective mass as a fitting parameter. The performance of the multivalley ECBE method is tested using an ensemble MC simulator to study benchmark devices for next International Technology Roadmap for Semiconductors technological nodes, a 25-nm channel length bulk-MOSFET and a double-gate silicon-on-insulator MOSFET in both steady-state and transient situations

Equivalent Oxide Thickness of Trigate SOI MOSFETs With High-

The evolution of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) from planar single-gate devices into 3-D ones with multiple gates and high-kappa insulators imposes the use of new electrical models that accurately reproduce their behavior. This paper demonstrates that the typical expression of equivalent oxide thickness (EOT) for planar devices with high- kappa gate insulators becomes useless for nonplanar ones such as triple-gate (trigate) silicon-on-insulator MOSFETs. An alternative expression of the EOT for these trigate devices has been developed through a semianalytical approach to the gate-insulator capacitance. The proposed model correctly reproduces the total electron density in a wide range of device dimensions and applied biases.

\kappa

Graphene/silicon (G/Si) heterojunction based devices have been demonstrated as high responsivity photodetectors that are potentially compatible with semiconductor technology. Such G/Si Schottky junction diodes are typically in parallel with gated G/silicon dioxide (SiO2)/Si areas, where the graphene is contacted. Here, we utilize scanning photocurrent measurements to investigate the spatial distribution and explain the physical origin of photocurrent generation in these devices. We observe distinctly higher photocurrents underneath the isolating region of graphene on SiO2 adjacent to the Schottky junction of G/Si. A certain threshold voltage (VT) is required before this can be observed, and its origins are similar to that of the threshold voltage in metal oxide semiconductor field effect transistors. A physical model serves to explain the large photocurrents underneath SiO2 by the formation of an inversion layer in Si. Our findings contribute to a basic understanding of graphene/semiconductor hybrid devices which, in turn, can help in designing efficient optoelectronic devices and systems based on such 2D/3D heterojunctions.

Insulators

In this paper, we propose a physically based analytical model for the gate capacitance (CG) of III-V nanowire (NW) transistors. The model explicitly accounts for different terms that contribute to CG: the insulator capacitance, the finite density of states, and the charge distribution in the NW. It considers the 2-D quantum confinement of the carriers, the wavefunction penetration into the gate insulator, Fermi-Dirac statistics and the conduction band nonparabolicity, providing analytical expressions for all the capacitance contributions. Furthermore, the behavior and role of the density of states and the charge distribution in the NW are discussed for several materials and the influence of the wavefunction penetration into the gate insulator is also studied. We show that our analytical model is in very good agreement with the numerical solution for different device sizes and materials.

High Photocurrent in Gated Graphene–Silicon Hybrid Photodiodes

We present an extension of the unscreened generalized Prange-Nee term used to calculate the surface roughness (SR) limited mobility in arbitrarily oriented square nanowires. The presence of non-diagonal terms in the effective mass tensor is responsible for an additional term not considered in previous studies. We assess the impact of such a modification on the SR limited mobility and on the total mobility (SR and phonon scattering are considered) for devices with different orientation and size. We show that this impact is more relevant for small devices, where the SR plays an important role, even at low inversion charge.

Analytical Gate Capacitance Modeling of III–V Nanowire Transistors

In this work, an analytical model is proposed to calculate the potential and the inversion charge of III-V cylindrical Surrounding-Gate metal-oxide-semiconductor field-effect transistors (MOSFETs). The model provides expressions for the calculation of the subband energies and their corresponding wavefunctions, taking into account their penetration into the gate insulator and the effective mass discontinuity in the semiconductor-insulator interface for this kind of devices. The model considers Fermi-Dirac statistics and the two-dimensional quantum confinement of the carriers. We demonstrate that our analytical solution fits very well the numerical solution in all operating regimes and for different device sizes and materials.

Surface roughness scattering model for arbitrarily oriented silicon nanowires

In this paper, the effects of device orientation, geometry, and strain (uniaxial and biaxial) on the electrostatic properties of different silicon gate-all-around metal-oxide-semiconductor field-effect transistors are thoroughly investigated. We show how the electron density changes with the device orientation and how it depends on the geometry, size, and strain. Although the threshold voltage is weakly dependent on the orientation, we show that it is strongly affected by the geometry, strain, and size. In addition, the suitability of the isotropic effective mass model is investigated for cylindrical devices. We prove that this model is not able to mimic electron density obtained with a nonisotropic model. However, if an appropriate isotropic effective mass value is selected, the behavior of the threshold voltage can be reproduced.

Analytic potential and charge model for III-V surrounding gate metal-oxide-semiconductor field-effect transistors

This work studies the electron mobility in InAs nanowires (NWs), by solving the Boltzmann Transport Equation under the Momentum Relaxation Time approximation. The numerical solver takes into account the contribution of the main scattering mechanisms present in III-V compound semiconductors. It is validated against experimental field effect-mobility results, showing a very good agreement. The mobility dependence on the nanowire diameter and carrier density is analyzed. It is found that surface roughness and polar optical phonons are the scattering mechanisms that mainly limit the mobility behavior. Finally, we explain the origin of the oscillations observed in the mobility of small NWs at high electric fields.

Influence of Orientation, Geometry, and Strain on Electron Distribution in Silicon Gate-All-Around (GAA) MOSFETs

In this work, we develop a comprehensive model of the total gate capacitance (C_G) of circular-cross-section surrounding gate transistors that accounts for both the insulator gate capacitance (C_ins) and the inversion capacitance (C_inv). The accuracy of the model is checked with the results obtained from the numerical simulation of the structure. Using this model, we compare the C_G/C_ins ratio with that of double-gate (DG) transistors and study the degradation of the total gate capacitance of both devices as a function of the gate voltage and device size. It is shown that the C_G/C_ins ratio is higher in DGs, particularly for very small devices.