F.H. Gaensslen

Very small MOSFET's for low-temperature operation

The improvements in the device characteristics of n-channel MOSFETs that occur at low temperatures are considered in this paper. The device parameters for polysilicon gate FETs with channel lengths of the order of 1 µm have been studied both experimentally and theoretically at temperatures ranging from room temperature down to liquid nitrogen temperature. Excellent agreement was found between the experimental dc device characteristics and those predicted by a two-dimensional current transport model, indicating that device behavior is well understood and predictable over this entire temperature range. A device design is presented for an enhancement mode FET with a channel length of I µm that is suitable for operation at liquid nitrogen temperature.

1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications

Micrometer-dimension n-channel silicon-gate MOSFETs optimized for high-performance logic applications have been designed and characterized for both room-temperature and liquid-nitrogen-temperature operation. Appropriate choices of design parameters are shown to give proper device thresholds which are reasonably independent of channel length and width. Depletion-type devices are characterized at room temperature for load device use. Logic performance capability is demonstrated by test results on NOR circuits for representative fan-out and loading conditions. Unloaded ring oscillators achieved switching delays down to 240 ps at room temperature and down to 100 ps at liquid nitrogen temperature.

Simulation of impurity freezeout through numerical solution of Poisson's equation with application to MOS device behavior

Incorporation of temperature dependencies in the one-dimensional Poissons equation for use in numerical simulation of MOSFET threshold behavior from 350 to 50 K is discussed. Careful consideration has been given to accurate modeling of impurity freeze-out and temperature-dependent parameters. Examples of simulation of depletion-mode MOSFETs demonstrate the importance of proper modeling and show that impurity freezeout must be considered even at room temperature.

Low temperature threshold behavior of depletion mode devices—Characterization and simulation

INTRODUCTION The changes in threshold voltage characteristics observed between room and liquid nitrogen temperature for depletion and enhancement mode MOS devices are fundamentally different. As described elsewhere (I), the enhancement mode threshold voltage is not affected by carrier freezeout; it shows only an increase in magnitude due to temperature dependent parameter changes combined with an essentially unaltered substrate sensitivity. Actual measurements of depletion mode devices, however, show a significantly different temperature dependency. With decreasing temperature, the negative threshold voltage shift, usually achieved by a shallow donor implantation within an n-channel technology, is reduced as is the substrate sensitivity. Both changes can be accounted for by freezeout within the shallow, compensated, n-type surface layer.

An Efficient Numerical Algorithm for Simulation of MOS Capacitance

A new, computationally efficient method for the numerical evaluation of the equilibrium capacitance of one-dimensional MOS structures is presented. Capacitance-voltage (C-V) characteristics for arbitary impurity profiles and interface state distributions can be calculated for temperatures ranging from 50 K to 350 K. Examples of simulated C-V characteristics demonstrate the capability of the computer program MOSCAP using these techniques.

Low temperature semiconductor electronics

The authors consider that, at any technology level, operation at liquid nitrogen temperature (LNT: 77.3 K) can directly yield a performance improvement exceeding that provided through down-scaling by a factor of two. Thus, MOS technology limits are extended by one generation through LNT operation. Because of its attractive speed, density, and power attributes, liquid-nitrogen-cooled CMOS represents a strategic technology alternative for mainframe computers, an area which has traditionally been the exclusive domain of bipolar technology. A summary of the advantages for MOS microelectronics operated at LNT is presented in a table and discussed.<<ETX>>

Simple analytical models for the temperature dependent threshold behavior of depletion-mode devices

Threshold voltage shifts in ion-implanted depletion-mode MOSFETs depart substantially from the usual dose proportional shift of enhancement-mode devices. Analytic expressions for the relationship between threshold voltage shift and implanted donor dose and position are extended to include impurity freezeout at low temperatures, and a simple model for the observed low substrate sensitivity at low temperature is presented. Criteria to avoid parasitic subthreshold conduction in depletion-mode devices are also established using the threshold shift formulation.

Liquid nitrogen CMOS for computer applications

Past and present development in the field of operating microelectronic computer circuits at liquid nitrogen temperature (LNT) are reviewed. To assess the potential of this technology, its advantages and disadvantages are discussed. The fact that devices and materials behave generically better at low temperature will have some bearing on the ultimate attainable technology limits. The optimized complementary metal oxide semiconductor (CMOS) system advantages at LNT are analyzed. The basic conclusion is that the liquid nitrogen CMOS (LNCMOS) is a viable system technology for commercial and military computer systems.<<ETX>>

Low power MOSFET memory cells using Schottky-barrier diodes

Joint integration of n-channel MOSFETs and Schottky-Barrier diodes (SBD) requires only modest changes in the overall FET process but offers considerable improvements over all-FET circuits in power consumption, density and performance. To implement SBDs n+pockets are outdiffused through a p-type epitaxial layer and put in contact with the proper metal. MOS guard rings are utilized to relieve electrical field enhancement around the perimeter of the device.

Anomalous MOS capacitance behavior in depletion-mode structures

Room-temperature and liquid-nitrogen temperature capacitance measurements on enclosed-channel depletion-mode structures have shown anomalous behavior in the accumulation region of operation. Simulation has shown that the potential minimum in the buried channel of the depletion-mode device prevents high frequency variation in the accumulation-layer hole concentration. It is postulated that similar effects may be expected in depletion-mode devices using recessed oxide isolation.