Lewis M. Terman

A 1 mV MOS comparator

An MOS comparator circuit capable of detecting difference signals as low as 1 mV in 3 /spl mu/s has been designed, built, and tested. The circuit does not require high accuracy components or tight control of device parameter tolerances.A MOS comparator circuit capable of detecting + 1 mV difference signals in 3 ¿s has been designed and tested. The circuit does not require high accuracy components or tight control of device parameter tolerences.

A two-stage weighted capacitor network for D/A-A/D conversion

A two-stage weighted capacitor network for A/D and D/A conversion utilizing a feedback amplifier is described. The two-stage weighted capacitor DAC requires a smaller range of capacitor values then the conventional weighted capacitor DAC and is not subject to the nonlinear effects of parasitic capacitance. Experimental results of such a DAC implemented using a conventional n-channel metal-gate MOS process are presented. A discussion of the comparative accuracy and area of one- and two-stage weighted capacitor DACs on the basis of capacitor tracking is given.

MOSFET memory circuits

Metal-oxide-semiconductor first effect transistors (MOSFETs) are currently being used in a variety of memory applications. The requirements of memory usage and the characteristics of MOSFET devices and technology have led to a number of unique circuits for these applications. Organization and design considerations of memory systems using MOSFET devices are reviewed, and examples of specific circuits are presented and analyzed. These include random access cells, shift registers, read only storage, and on-chip support circuits; both complementary and noncomplementary circuits are discussed.

A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate

The authors describe a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM cell. The 128-kb*4, 78-mm/sup 2/ chip shows a random access time of 20 ns and a column access time of 7.5 ns, measured at 5.0 V, 25 degrees C, and 50-pF load. A 256-b*4 high-speed page mode is provided which has 12-ns cycle into 60 pF, resulting in a data rate of 330 Mb/s. Additional measurements on HSDRAM further demonstrate that DRAM operation in a high-speed regime is not precluded by noise, power, wiring delay, and soft error rate. The device is implemented in a 1.0 mu m n-well CMOS process. >

An Investigation of the Potential of MOS Transistor Memories

The design and performance characteristics of a 128X64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time.

CCD memory using multilevel storage

CCD multilevel storage resulting in increased bit density and decreased sense signal, will be reported, citing design considerations for multilevel storage. Launch and sense circuits which are insensitive to geometry and parameter tolerances will be presented.

The effect of alpha-particle-induced soft errors on memory systems with error correction

Using Poisson statistics, a model for the survival probability of a memory system having both hard and soft error bit failure mechanisms is developed. Calculations are made over a range of soft error generation rates and erasure intervals for both single and double error correction.

The impact of device scaling limits

The semiconductor market has been experiencing remarkable expansion, with a CGR approaching 30% over the last half decade. This growth has been driven by continuing device miniaturization and the attendant increase in integration level and performance and decrease in cost. However, as devices become smaller, there is concern that fundamental limits will restrict further progress. Possible fundamental limits to device miniaturization and chip performance are considered. It is shown that while there are such limits, devices into the deep sub-0.1 mm region with acceptable characteristics could be built, providing that practical considerations in such areas as fabrication and lithography, design complexity, interconnect delay and fabrication facility cost can be overcome.

Overview of CCD memory

This paper summarizes the status and potential of charge-coupled device (CCD) memories. Cost-performance tradeoffs for serial memories are reviewed, and the CCD chip organizations for slow and fast access systems are discussed. Comparisons are made between CCD and MOS random access memory (RAM) chips on the basis of cell area, support circuits, cell operation, and technology.

A variable precharge voltage sensing

A new DRAM sensing approach that uses variable precharge voltage has been developed and analyzed in simulations. It uses a voltage swing only on the bit-line connected to the accessed cell. The bit-line precharge voltage varies from one RAS cycle to the next, depending on the level of the data in the accessed cell. The reference voltage for bit-line sensing is given by a new reference-cell control circuit without using a reference-voltage generator. The current required for sensing decreases as the precharge voltage increases, resulting in reduced power without any reduction of the sensing signal. Detailed analysis shows that the sensing current is only 2/3 of that in 1/2 T/sub DD/ sensing, even in the worst case. >