Jean-Michel Sallese

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm-3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

Global Modeling Strategy of Parasitic Coupled Currents Induced by Minority-Carrier Propagation in Semiconductor Substrates

This paper presents a modeling strategy to simulate the propagation of electrical perturbations induced by direct biasing of substrate junctions. Usually, this is done by identifying parasitic substrate devices such as bipolar transistors. However, mapping a topology with these bipolar transistors rapidly reaches its limits when several junctions are acting at the same time. In this paper, we propose a new modeling methodology of parasitic signals. It relies on a generalized model of p-n junctions and resistances that takes into account minority-carrier densities and gradients at the boundaries. We show that bipolar-transistor- and thyristor-related effects can be obtained from a network interconnection of these extended devices. Furthermore, we show that this modeling approach could be easily extended to simulate complex 3-D layouts.

Generalization of the Concept of Equivalent Thickness and Capacitance to Multigate MOSFETs Modeling

In this letter, we propose to introduce the notion of equivalent capacitance and to generalize the so-called equivalent-thickness concept to model arbitrary shapes of lightly doped nonplanar multigate MOSFETs, without the need to introduce any unphysical parameter. These definitions, which merely map a multigate geometry into the symmetric double-gate (DG) MOSFET topology, have been validated by extensive comparison with 3-D numerical simulations of quadruple-gate, triple-gate (TG), triangular gate, cylindrical gate-all-around, and DG Fin Field Effect Transistors (FinFETs). Based on this modeling approach, any multigate architecture inherits of the fundamental relationships that have been developed for planar DG MOSFETs, including the normalization of all electrical quantities that considerably simplifies its analysis. In addition, considering a constant mobility, we find that the model can predict electrical characteristics of FinFETs from 275 to 425 K, without the need for any additional parameters. Finally, we were able to predict electrical measurements of a TG MOSFET, making of this generic model an interesting candidate for a design-oriented compact model for arbitrary multigate MOSFETs geometries.

A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET

This paper presents a novel physics-based analytical compact model for the drift region of a high-voltage metal-oxide-semiconductor field-effect transistor (HV-MOSFET). According to this model, the drift region is considered as a simple 1-D problem, just as that of a low-voltage inner MOS transistor. It exploits the charge-sheet approximation and performs linearization between the charge in the drift region and the surface potential. The drift region model combined with the standard charge-sheet MOS model for the low-voltage part adds up to a complete HV-MOSFET model, which is verified against technology computer-aided design simulations and measurements of HV-MOS transistors. The comparisons demonstrate its accurate physics foundations and underline that this novel approach to the modeling of the drift region of the HV-MOSFET is promising.

Transient Off-Current in Junctionless FETs

We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless field-effect transistors. This effect might be attributed to a process involving generation of holes in the n-type-doped channel, which can also explain the partial channel depletion as consequence of channel screening by an inversion layer, thus impeding the device to be switched off. The approach described in this work could also be used for characterization of silicon channels in junctionless nanowires.

Compact modeling of gate sidewall capacitance of DG-MOSFET

Recent studies show that the gate sidewall capacitance of an underlap double gate device plays an important role in the design and optimization of the device. To date, only semiempirical techniques are used to model this important capacitance. In this brief, the authors present an analytical model of the fringe capacitance and find out a geometry dependent quantity which determines the scaling of this capacitance

Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage H-bridge at High Temperature

In this paper, a modeling methodology is validated based on an enhanced model of the diode, that we have developed to simulate substrate current coupling mechanisms on a typical H -bridge structure. An equivalent schematic based on an enhanced model of the diode was previously proposed to account for minority and majority carrier propagation in the substrate and implemented in Verilog-A code. In this study, the injected parasitic substrate current from high-voltage MOSFETs structure is simulated in a circuit-level simulator and with a finite element method, as well. Both are compared to measurements and confirm a very good agreement up to 400 K. Not only the simulation resources needed by the proposed equivalent schematics are greatly reduced with regard to the finite element approach, but this circuit-level modeling methodology is fully compatible with Spice-like simulations of complex ICs.

EKV compact model extension for HV lateral DMOS transistors

This paper reports for the first time on the extension of the EKV compact model for high-voltage (HV) MOSFETs. A continuous expression is derived for the drift bias-dependent resistance of DMOS transistors and then validated in different operation regions (in linear and saturation regimes). When combined with EKV, the proposed new drift model provides very accurate DC modeling including quasi-saturation.

Modeling the Channel Charge and Potential in Quasi-Ballistic Nanoscale Double-Gate MOSFETs

In this paper, we present an analytical semiempirical model of the profile of the channel charge and potential in quasi-ballistic double-gate (DG) MOSFETs. The charge model is based on the premise of separating the charge density in the quasi-ballistic channel into two hypothetical components: 1) exclusively ballistic (collision-free) and 2) collision-dominated components, which are governed by the same electrostatics. These components are related to each other through a ballisticity parameter whose values lie between 0 and 1. Varying the value of this parameter allows us to model the charge profile continuously between diffusive and purely ballistic devices. Using the proposed charge model and the DG MOSFET electrostatics, an analytical expression for the channel potential is derived which, like the charge model, is continuous between the diffusive and ballistic regimes.

Measurement and Compact Modeling of 1/f Noise in HV-MOSFETs

This paper investigates 1/f noise behavior under low and high drain biases of high-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) (HV-MOSFETs). A dedicated setup is presented which allows measuring low-frequency (LF) noise of lateral double-diffused MOSFETs (LDMOSFETs) up to 200 V at the drain. LF noise spectra of n- and p-channel LDMOSFETs were measured over a large range of gate and drain bias conditions and modeled using a recently established physics-based compact model of HV-MOSFETs. The investigated devices confirm that the overall noise is mostly dominated by the noise originating in the channel, while the drift-region-generated noise only is apparent in linear operation.