Takeshi Akatsu

Study of extended-defect formation in Ge and Si after H ion implantation

Extended defects formed after hydrogen implantation into Si and Ge (100) substrates and subsequent thermal anneals were investigated by transmission electron microscopy. The majority of the extended defects formed in both materials were platelet-like structures lying on {100} and {111} planes. We found {100} platelets not only parallel but also perpendicular to the surface. In Ge wafers, high density of {311} defects and nanobubbles with the average size of 2 nm were observed. The difference between two materials can be attributed to the weaker strength of Ge–H bond.

Mechanism of the Smart Cut™ layer transfer in silicon by hydrogen and helium coimplantation in the medium dose range

We investigate the mechanism of the Si layer transfer in the Smart Cut™ technology for H and He coimplantation in the dose range of (2.5–5)×1016cm−2. Using infrared spectroscopy and cross-section transmission electron microscopy we study the microstructure of defects formed in Si in the as-implanted state. With H preimplant we observe significant enhancement of damage production as compared to the case where He is implanted first. At higher coimplant doses a buried nonuniform amorphouslike layer is formed. The structure of the layer resembles “swiss cheese” with highly damaged but still crystalline pockets embedded into amorphous material. The effect of coimplantation parameters on the thickness and crystal quality of transferred layer is discussed in the framework of a simple phenomenological model.

200mm germanium-on-insulator (GeOI) by Smart Cut/spl trade/ technology and recent GeOI pMOSFETs achievements

We present our recent achievements on 200mm GeOI formation from bulk Ge wafers and the resulting device characteristics. Pseudo-MOS measurements were done at Soitec, and Ge MOSFET fabrication was done at LETI and IMEC from epitaxial and bulk Ge starting materials, respectively.

Chapter 1 – Germanium Materials

Publisher Summary This chapter discusses germanium (Ge) fabrication techniques. Other than the manufacturing of Czochralski Ge substrates, this chapter also discusses the possible approaches for making germanium-on-insulator (GOI) materials. The chapter reviews the present status and future outlook for 200 and 300 mm wafers. Although at the early transistor technology development, the quality of Ge crystals was far better than thos of Silicon (Si), Si has been dominating the semiconductor market for the past 40 years. Ge material improvements have been focusing on other market segments–– such as detectors and solar cells. However, because of the potential revival of Ge for deep submicron complementary-metal-oxide-semiconductor (CMOS) applications, much effort has been devoted in recent years to fabricate high-quality 200 and 300 mm Ge wafers.

Ge Diffusion in Strained Si / Relaxed SiGe Heterostrucutures

We have studied the Ge diffusion in strained silicon (sSi) layers deposited on SiGe virtual substrates. Two Ge concentrations have been used to induce strain in the Si layers: 30 and 40%, corresponding to a 1.8 and 2.5 GPa strain level respectively. Ge diffusion in highly strained layers has been understudied, whereas these layers are of great interest since they allow mobility gains for both electrons and holes. Therefore, quantifying the impact of Ge diffusion within the sSi layer (sSi consumption, Ge doping and piling...) is of great importance if one wants to use such layers for CMOS transistors or for the realization of strained Silicon On Insulator wafers using the SmartCut technology. The samples consist in a deposited SiO2 / sSi / relaxed SiGe / graded buffer / Si substrate stack. Thermal treatments have been performed in a horizontal furnace with temperatures ranging from 750 up to 1000°C. The Ge diffusion in sSi has been characterized by Secondary Ion Mass Spectrometry (SIMS). Figure 1 shows the Ge concentration depth profile in a sSi layer deposited on relaxed Si0.7Ge0.3 for the various thermal treatments investigated.

Fracture in Hydrogen‐Implanted Germanium

We have studied the mechanism of fracture in hydrogen‐implanted Ge. First, the as‐implanted Ge state and its evolution during subsequent annealing were characterized via TEM and FTIR‐MIR spectroscopy. Results showed that the extended defects formation and growth follow the same basic mechanism in Ge as in Si, which is the reference material. Nevertheless, the global damage level in the implanted Ge layer is higher compared to Si. Second, the fracture step was studied via the fracture kinetics analysis, SIMS and AFM on the transferred layer. An activation energy comparable to the reported data from blistering studies was obtained. Just like in Si, the Cmax of H in Ge measured via SIMS was found to decrease during the fracture anneal. This decrease is associated with the formation of gaseous H2 that pressurizes the internal cavities and then contributes to the fracture. Finally, a high roughness of the Ge transferred layer was measured, which results from the large thickness of the implantation damaged zone.

Germanium Deep-Submicron p -FET and n -FET Devices, Fabricated on Germanium-On-Insulator Substrates

A key challenge in the engineering of Ge MOSFETs is to develop a proper Ge surface passivation technique prior to high-κ dielectric deposition to obtain low interface state density and high carrier mobility. A review on some possible treatments to passivate the Ge surface is discussed. Another important aspect is the activation of p- and n-type dopants to form the active areas in devices. Finally, Ge deep submicron n- and p-FET devices fabricated with this technique on germanium-on-insulator substrates, yield promising device characteristics, showing the feasibility of these substrates.

Advanced High-Mobility Semiconductor-on-Insulator Materials

Silicon-on-Insulator (SOI) is today the substrate of choice for several applications. In order to boost further circuit performance, new solutions are being explored. In particular, increasing the charge carrier mobility has been identified as a requirement for the next technology nodes. One possible option is to increase transistor channel mobility through local strain engineering via external Stressors, an approach that can be used on bulk silicon as well as standard SOI substrates. Other solutions are based on substrate engineering. The attractiveness of these solutions is largely due to their compatibility with standard CMOS integration processes and architectures and presents the advantage of being independent of transistor geometry. The two approaches can be combined to maximize transistor mobility and on-current. Among the different substrate level approaches, we will focus on three main families: (1) the effect of crystal orientation, (2) strained Si and/or SiGe layers On Insulator, and (3) monocrystalline Ge-On-Insulator substrates.

Smart Cut/spl trade/ transfer of 300 mm [110] and (100) Si layers for hybrid orientation technology

In hybrid-orientation technology (HOT), devices are fabricated on hybrid substrate with [110] and (100) orientations to achieve significant PMOS performance enhancement. Smart cut process is an important step in the substrate engineering for HOT. We investigate the details of layer transfer in the substrates of different orientations and presents the characteristics of product [110] SOI wafers. For the first time, we show that H platelet distributions, splitting kinetics and evolution of post-split surface morphology demonstrate strong substrate orientation dependence. Certain modifications of critical process steps in generic smart cut process flow are required to fabricate high quality [110] SOI wafers.