Fabrice Seguin

A gain-controllable wide-band low-noise amplifier in low-cost 0.8-/spl mu/m Si BiCMOS technology

A low-noise amplifier (LNA) implemented in a low-cost Si-BiCMOS 0.8-/spl mu/m process is presented. It utilizes current conveyors as building blocks. The principle and design methodology are presented, followed by results obtained from simulations. A brief technology and measurement technique description is then made, leading up to the measurement results obtained. The performance is compared with some other LNA realizations. The potentialities of the LNA are finally touched upon, with particular regard to future communications systems. The gain of the LNA is controllable, in the range of 0-20 dB, by varying the dc bias current. Negative decibel gains can also be obtained, making it an attenuator circuit. Using a /spl plusmn/1.5 V supply, and at a measured gain of 14 dB, the LNA has measured -3 dB bandwidth of dc to 1.9 GHz, |Z/sub IN/| = 50 /spl Omega/, |S/sub 11/| = -21 dB, and a simulated noise figure = 3.3 dB, input P/sub 1dB/ = -33 dBm, and consumes only 3.8 mA. A judicious tradeoff between the decibel gain and bandwidth yields -3 dB bandwidths of up to 5.5 GHz, while in the -10-dB cutoff specified for ultra-wide-band (UWB) systems, passbands greater than 10 GHz are enabled. The LNA occupies 0.24 mm/sup 2/ of chip area, including pads. The prospective applications range from current global system for mobile communications, code division multiple access, and multiband systems, to the upcoming UWB.

Semi-Iterative Analog Turbo Decoding

Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performance. The proposed algorithm and architecture are applied to design an analog decoder for double-binary codes. Taking full advantage of multiple slice codes, the on-chip area is shown to be reduced by ten when compared to a conventional fully parallelized analog slice turbo decoder. The reconfigurable analog core area for frames of 40 bits up to 2432 bits is 37 nm2 in a 0.25-mum BiCMOS process.