Cyril Lahuec

A Multi-Band Stacked RF Energy Harvester With RF-to-DC Efficiency Up to 84%

The aim of this paper is to show the possibility to harvest RF energy to supply wireless sensor networks in an outdoor environment. In those conditions, the number of existing RF bands is unpredictable. The RF circuit has to harvest all the potential RF energy present and cannot be designed for a single RF tone. In this paper, the designed RF harvester adds powers coming from an unlimited number of sub-frequency bands. The harvesters output voltage ratios increase with the number of RF bands. As an application example, a 4-RF band rectenna is designed. The system harvests energy from GSM900 (Global System for Mobile Communications), GSM1800, UMTS (Universal Mobile Telecommunications System) and WiFi bands simultaneously. RF-to-dc conversion efficiency is measured at 62% for a cumulative -10-dBm input power homogeneously widespread over the four RF bands and reaches 84% at 5.8 dBm. The relative error between the measured dc output power with all four RF bands on and the ideal sum of each of the four RF bands power contribution is less than 3%. It is shown that the RF-to-dc conversion efficiency is more than doubled compared to that measured with a single RF source, thanks to the proposed rectifier architecture.

Stochastic Multiple Stream Decoding of Cortex Codes

Being one of the most efficient solutions to implement forward error correction (FEC) decoders based on belief propagation, stochastic processing is thus a method worthy of consideration when addressing the decoding of emerging codes such as Cortex codes. This code family offers short block codes with large Hamming distances. Unfortunately, their construction introduces many hidden variables making them difficult to be efficiently decoded with digital circuits implementing the Sum-Product algorithm. With the introduction of multiple stochastic streams, the proposed solution alleviates the hidden variables problem thus yielding decoding performances close to optimal. Morevover, this new stochastic architecture is more efficient in terms of complexity-throughput ratio compared to recently published stochastic decoders using either edge or tracking forecast memories.

A Self-Powered Telemetry System to Estimate the Postoperative Instability of a Knee Implant

Estimating in vivo the life span of a total knee replacement prosthesis is currently done by estimating the polyethylene (PE) wear rate from measurement of the femorotibial distance using X-ray photographies. This efficient method requires, however, waiting for few years to obtain a readout. This letter proposes using another metric that can be obtained within a couple of months of surgery, namely the center of pressure (COP). This metric represents the point, where the axial force applies the most onto the tibial tray. The displacement of the COP with respect to its ideal position can be used to estimate the wear and the life span of the PE. This requires the implant to be fitted with a telemetry system described briefly. The proposed method is supported by measures and simulations.

Scaling of analog LDPC decoders in sub-100nm CMOS processes

Analog implementations of digital error control decoders, generally referred to as analog decoding, have recently been proposed as an energy and area competitive methodology. Despite several successful implementations of small analog error control decoders, little is currently known about how this methodology scales to smaller process technologies and copes with the non-idealities of nano-scale transistor sizing. A comprehensive analysis of the potential of sub-threshold analog decoding is examined in this paper. It is shown that mismatch effects dominated by threshold mismatch impose firm lower limits on the sizes of transistors. The effect of various forms of leakage currents is also investigated and minimal leakage current to normalizing currents are found using density evolution and control simulations. Finally, the convergence speed of analog decoders is examined via a density evolution approach. The results are compiled and predictions are given which show that process scaling below 90nm processes brings no advantages, and, in some cases, may even degrade performance or increase required resources.

Analog slice turbo decoding

This paper presents the design of an analog turbo decoder for DVB-RCS-like applications using a slice architecture. The constituent decoders for different frame lengths are made up of duplicated elements chosen from a small set of reduced-size MAP decoders. This slicing technique enhances the design of the decoder in terms of simplicity, testability, re-usability and robustness. It is illustrated with the example of a turbo decoder for frames of 48 symbols sliced into two sub-frames. The error correction performance of this analog slice decoder is equal to that of the digital counterpart without slices. Transistor-level simulations show a potential throughput up to 1.5Gb/s for a 2.9mW core power consumption per information bit and per state in a 0.25/spl mu/m BiCMOS process.

Semi-iterative analog turbo decoding

This paper presents a novel analog turbo decoding architecture allowing analog decoders for long frame lengths to be implemented on a single chip. This is made possible by suitably using slicing techniques which allow hardware reuse and reconfigurability. The architecture is applied to a DVB-RCS-like code. It shows a reduction of occupied chip area by a factor of ten when compared to a conventional slice design with no significant performance degradation. A single 27mm2 0.25mum BiCMOS decoder can then decode any frame length from 40 up to 1824 bits

A multi-tone RF energy harvester in body sensor area network context

A wide-band 900 MHz to 2.45 GHz rectenna has been developed for Radio Frequency (RF) energy harvesting in the context of outdoors Wireless Sensor Nodes (WSN). Based on simulations of different rectifying circuits, the most appropriate one for low incident power levels has been manufactured and tested with a wide-band antenna. The theoretical analysis, confirmed by measurements, shows that the proposed method yields a 20% increase in average in the DC output voltage compared to a single frequency system.

A ligament laxity telemetry system architecture for a knee replacement prosthesis

In this paper the feasibility of a novel instrumented orthopaedic implant for total knee replacement is studied. The system aims at providing an indication on the balance of the lateral ligaments. The measures will be used to estimate the wear out of the polyethylene part of the prosthesis and will also facilitate the patient rehab. The data will be transmitted outside the body through an RF link. Unlike other instrumented implants, the system will be self-powered. Piezo ceramics will be used both as pressure sensors and as power generators. This implies that the measurement system must be ultra low power as the available power is less than 1.8 mW. First simulation results are given for a 0.35 ¿m CMOS process.

Ultra-Low-Energy Mixed-Signal IC Implementing Encoded Neural Networks

Encoded Neural Networks (ENNs) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks (HNNs) for the same number of nodes. Moreover, they have a lower density than HNNs in terms of connections, allowing a low-complexity circuit integration. The implementation of such a network requires low-complexity elements to take complete advantage of the assets of the model. This paper proposes an analog implementation of the ENNs. It is shown that this type of implementation is suitable for building network of thousands of nodes. To validate the proposed implementation, a prototype ENN of 30 computation nodes is designed, fabricated and tested on-chip for the ST 65-nm 1-V supply complementary metal-oxide silicon (CMOS) process. The circuit shows decoding performance similar to that of the theoretical model, and decodes a message in 58 ns. Moreover, the entire network occupies a silicon area of 16470 μm2 and consumes 145 μW, yielding a measured energy consumption per synaptic event per computation node of 68 fJ.

Effect of BJT’s parasitics on computing cells for analog decoders

This paper analyzes the effect of inherent bipolar transistor parasitic elements on the computing nodes performance used in BJT analog decoders. It is shown that these undesirable effects significantly degrade, up to 85%, the conversion of Log-Likelihood Ratios into probabilities. This can lead to a wrong decoding outcome when complex computing nodes are designed. Simulation results are shown for a 0.25-mum BiCMOS process from NXP.