Alvernon Walker

Fault diagnosis in analog circuits using element modulation

Analog fault diagnostic methods are reviewed. A branch fault-diagnosis technique that requires a single excitation source at one test frequency is introduced. The technique lets users construct linearly independent branch-diagnosis equations by modulating selected network elements. An example of the technique applied to a two-stage amplifier is given.<<ETX>>

An approach for detecting bridging fault-induced delay faults in static CMOS circuits using dynamic power supply current monitoring

A new approach for the detection of bridging fault-induced delay faults in static CMOS logic circuits is presented in this paper. It is based upon the transient current that is sourced (or sink) by the power supply (or ground) rail of a primary output gate during a low-to-high (or high-to-low) output transition. We show that the dynamic power supply current (DPSC) can be used to detect delay faults that are due to bridging faults because the DPSC is a function of the parameters and the interconnectivity of the transistors that form the discharge/charge circuits in the gates along the path-under-test. An example of a dynamic power supply current monitoring circuit is also presented. The paper is concluded with an example of the application of the proposed approach for detecting bridging faults in static CMOS logic circuit.

On-line error detectable carry-free adder design

A technique for designing carry-free adders with on-line error checking capability is presented. The adders use signed binary digits (SBDs) internally. An adder consists of sign-magnitude binary to SBD converters, an intermediate adder block that generates partial sum and carry digits, a second adder block that produces a sum digit computed from a partial sum and a partial carry digit, and an error checker that indicates whether the code word corresponding to a final sum digit is error-free or not.

An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring

A new approach for the detection of bridging faults in CMOS domino logic circuits is presented in this paper. It is based upon the transient current that is sourced (or sink) by the power supply (or ground) rail of the inverter in the domino logic gate during a low-to-high (or high-to-low) output transition. We show that the dynamic power supply current can be used to detect bridging faults because it is a function of the parameters and the interconnectivity of the transistors that form the discharge/charge circuits in the gate-under-test. An example of a dynamic power supply current monitoring circuit is also presented. This paper is concluded with an example of the application of the proposed approach for detecting bridging faults in CMOS domino logic circuit.

A Fine Grain Configurable Logic Block for Self-checking FPGAs

This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexers and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults; otherwise the outputs are identical.

An on-line reconfigurable FPGA architecture

FPGAs are widely used for prototyping of digital systems. A major problem of current FPGA architectures is that if there is a fault in a single combinational logic block (CLB), it may take a significant amount of time to find an alternative mapping of the circuit to bypass the faulty block. Thus, there is a need for new type of FPGA architecture that allows rapid recovery from internal faults in a FPGA. Currently only the detection of permanent faults in logic blocks, and on their interconnections are considered in FPGA-based systems. Several studies in recent years have shown that transient faults are likely to occur at a much higher rate than permanent faults in submicron VLSI devices. The only way to cope with transient faults in FPGAs is to detect them as soon as they occur, and perform on-line reconfiguration to recover from their effects. This paper presents a reconfigurable FPGA architecture that enables on-line fault detection in the constituent CLBs of the FPGA.

A CMOS-based logic cell for the implementation of self-checking FPGAs

This paper proposes a logic cell that can be used as a building block for online testable FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch (DCVS) logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexer and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults or identical outputs in the presence of fault.

A unified scheme for designing testable state machines

An approach for designing state machines that have built-in on-line and off-line testability is proposed. The next state logic is designed using transmission gates and tri-state buffers only. The resulting machines have scan-in/scan-out capability that allows off-line testing of the next state logic. The on-line testing capability for erroneous state transitions is achieved by EX-ORing the outputs of two registers that store the current and the next state of a machine, and checking for even parity at the outputs of the EX-OR gates.

A technique for analog fault diagnosis using element modulation

The authors describe a novel branch fault-diagnosis technique which requires a single excitation source at one test frequency for solving branch-diagnosis equations. Linearly independent branch-diagnosis equations are constructed by modulating selected network elements. A network element whose value can be varied in a controlled fashion is defined as a modulated element. It is assumed for simplicity that all modulated devices in the network under test have two states (a state is a predefined element value). A subset of the network elements is modulated. Necessary and sufficient conditions for the diagnosis of at least q+1 branch elements at faulty circuit nodes have been derived for a general network where q network elements are modulated. An approximate upper bound on this system of equations is also derived. As an example, the proposed technique is applied to a resistive circuit.<<ETX>>

On Self-Checking Design of CMOS Circuits for Multiple Faults

A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption for the proposed technique. This paper also presents a technique for designing multistage TSC FCMOS circuits.