Parag K. Lala

Reversible-logic design with online testability

Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding

Carry-select adders are one of the faster types of adders. This paper proposes a scheme that encodes the sum bits using two-rail codes; the encoded sum bits are then checked by self-checking checkers. The multiplexers used in the adder are also totally self-checking. The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect all single stuck-at faults on-line; the detection of double faults is not guaranteed. Adders of arbitrary size can be constructed by cascading the appropriate number of such 2-bit adders. A range of adders from 4 to 128 bits is designed using this approach employing a 0.5-mum CMOS technology. The transistor overhead in implementing these self-checking adders varies from 19.51% to 20.94%, and the area overhead varies from 16.07% to 20.67% compared to adders without built-in self-checking capability.

Self-checking combinational circuit design for single and unidirectional multibit error

This article presents novel input and output encoding techniques such that the resulting circuit is bidirectional error-free. The circuit can be fully optimized and any types of gates can be used. These schemes are used to design the functional part of a self-checking circuit. The input encoding algorithm can be applied to any circuit without significantly increasing the input lines. The output encoding technique involves graph-embedding which is done with heuristic method of polynomial complexity. The heuristic technique produces nearly optimal output encoding. Previously published work restrict the types of gates used in the circuit to non-inversion gates (AND/OR), and use inverters only at the inputs. The proposed techniques have a clear advantage over the currently available techniques because they allow the use of any types of gates. These techniques do not necessarily increase the overhead when applied to different MCNC benchmark circuits as the experimental results indicate. The only restriction is that either the inputs or the outputs have to be symbolic, and the two-level description of a circuit has to be given.

Online testable reversible logic circuit design using NAND blocks

A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.

On-line testable logic design for FPGA implementation

In recent years, a number of logic design techniques for look-up table (LUT) based FPGAs have been proposed. However, none of these address issues such as fault detection or testability. This paper presents an algorithm which maps optimized Boolean expressions into look-up table based FPGAs. This mapping automatically incorporates testability features into designs, allowing on-line detection of faults within a FPGA. This is accomplished by utilizing a unique set of cells to implement a design. These cells operate on the premise of a two-rail checker, thus producing both the normal and complemented output when a cell is operating correctly, and two outputs of the same value in the presence of a fault. Faults generated in an intermediate cell is propagated to the final outputs, thus allowing on-line testability of a FPGA-based logic system.

Fault diagnosis in analog circuits using element modulation

Analog fault diagnostic methods are reviewed. A branch fault-diagnosis technique that requires a single excitation source at one test frequency is introduced. The technique lets users construct linearly independent branch-diagnosis equations by modulating selected network elements. An example of the technique applied to a two-stage amplifier is given.<<ETX>>

On-line detection of faults in carry-select adders

Paper 35.3 91 2 from the previous stage. If the actual carry-in is ‘0’ then the sum multiplexed from the first unit is selected, alternatively if the carry-in is. ‘ 1 ’ then the sum from the second unit is selected. A carry select adder of arbitrary size can be deigned by cascading together an appropriate number of such 4-bit adders. This paper concentrates on designing a scheme for implementing self-checking carry-select adders. Several techniques have been proposed in recent years for designing self-checking adders [2][3][4]. Coding techniques such as Berger code, Residue code and arithmetic codes have been proposed for checking the hnctionality of the arithmetic units. a3 b3 a2 b2 al b l QO bO

On self-healing digital system design

In recent years there has been a significant growth of interest in exploiting the principles of biological processes to create powerful methodologies for solving computational problems. This paper discusses how these features have been exploited in digital hardware design. It also introduces an architecture for implementing self-healing digital systems that is inspired by the antigen protection mechanism employed by the human immune system. In the proposed architecture, a spare cell is dedicated to replace one in a group of four functional cells. Once one of these four functional cells is found to be faulty, the spare cell is cloned as the faulty cell. This architecture is especially suitable for tolerating soft errors in functional cells or on interconnect lines. Another major advantage of this architecture is that the outputs of functional cells are connected to the inputs of other physically adjacent functional cells, thus making it appropriate for nanocomputing system design.

A novel approach for on-line testable reversible logic circuit design

Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.

An Architecture for Self-Healing Digital Systems

The use of very deep submicron technology makes VLSI-based digital systems more susceptible to transient or soft errors, and thus compromises their reliability. This paper proposes an architecture inspired by the human immune system that allows tolerance of such errors. An error in a digital system designed using the proposed architecture is treated as an antigen by the system. Using its distributed defense mechanism the system heals itself from the effect of the error. A major advantage of this architecture is that, the outputs of functional cells are connected to the inputs of other physically adjacent functional cells without having to go through complicated routing.