Fan Mo

PLA-based regular structures and their synthesis

Two regular circuit structures based on the programmable logic array (PLA) are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and simpler design methodologies. A whirlpool PLA is a cyclic four-level structure, which has a compact layout. Doppio-ESPRESSO, a four-level logic minimization algorithm, is developed for the synthesis of Whirlpool PLAs. A river PLA is a stack of multiple output PLAs, which uses river routing for the interconnections of the adjacent PLAs. A synthesis algorithm for river PLAs uses multilevel logic synthesis, simulated-annealing, and ESPRESSO targeting a combination of minimal area and delay.

Whirlpool PLAs: a regular logic structure and their synthesis

A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is logically a four-level Boolean NOR network. By arranging the four logic arrays in a cycle, a compact layout is achieved. Doppio-ESPRESSO, a four-level logic minimization algorithm is developed for WPLA synthesis. No technology mapping, placement or routing is necessary for the WPLA. Area and delay trade-off is absent, because these two goals are usually compatible in WPLA synthesis.

River PLAs: a regular circuit structure

A regular circuit structure called a River PLA and its re-configurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with standard-cells. Conventional optimization stages such as technology mapping, placement and routing are eliminated. These two features make the River PLA a highly predictable structure. Glacier PLAs can be an alternative to FPGAs, but with a simpler and more efficient design methodology.

A force-directed maze router

A new routing algorithm is presented. It is based on a multiple star net model, force-directed placement and maze searching techniques. The algorithm inherits the power of maze routing in that it is able to route complex layouts with various obstructions. The large memory requirement of the conventional maze algorithm is alleviated through successive net refinement, which constrains the maze searching to small regions. The algorithm shows advantages in routing designs with complicated layout obstructions.

Fishbone: a block-level placement and routing scheme

A block-level placement and routing scheme called Fishbone is presented. The routing uses a two-layer spine topology. The pin locations are configurable and restricted to certain routing grids in order to ensure full routability and precise predictability. With this scheme, exact net topologies are determined by pin positions only; hence during block placement, net parameters such as wire length (and delay) can be derived directly. The construction of Fishbone nets is much faster than for Steiner trees; this enables the integration of block placement and routing; there is no separate routing stage.

A timing-driven macro-cell placement algorithm

The timing-driven macro-cell placement algorithm described is based on the force-directed technique. The proposed star net model enables more accurate timing analysis, hence path delay constraints can be handled. In addition, the placer provides functions such as determination of cell orientation, routing estimation and pad placement. The algorithm is iterative and incremental, allowing flexibility in the physical design flow. The placer competes with commercial physical design tools and gives better results in terms of path delay.

Semi-detailed bus routing with variation reduction

A bus routing algorithm is presented which not only minimizes wire length but also selects the bits in the bus to avoid twisting and conflicts. The resulting bus routes are regular, thus having strong immunity to variations. Minimization for wire length/delay differences between different bits is also implemented.

A timing-driven module-based chip design flow

A Module-Based design flow for digital ICs with hard and soft modules is presented. Versions of the soft modules are implemented with different area/delay characteristics. The versions represent flexibility that can he used in the physical design to meet timing requirements. The flow aims at minimizing the clobk cycle of the chip while providing quicker turn-around time. Unreliable wiring estimation is eliminated and costly iterations are reduced resulting in substantial reductions in tun time as well as a significant decrease in the clock periods.

Placement based multiplier rewiring for cell-based designs

We present an algorithm for improving the performance of carry-save-adder (CSA) style multipliers. Based on placement information, the algorithm exploits the arithmetic equivalence in the CSA multipliers and rewires to improve the slack of the multiplier.

A simultaneous bus orientation and bused pin flipping algorithm

The orientation of a bus is defined as the direction from the least significant bit (LSB) to the most significant bit (MSB). Bused pin flipping is a property that allows several bused pins to flip without changing the system functionality. In this paper a simultaneous bus orientation and bused pin flipping algorithm is presented. The algorithm can be integrated into a bus-centric floorplanner targeting bus-rich designs such as microprocessors. Experimental results show that a floorplanner enhanced by the algorithm produces high quality floorplans in terms of bus routing.