Fan Xiao-ya

Dual-path architecture of floating-point dot product computation

Dot product computation is widely used in many algorithms, such as FFT and DCT. This paper proposes a floating-point dot product architecture based on the multiple-path method. This architecture could perform A × B+C × D as a single operation. The speed of the dual-path architecture implemented in single precision format is faster by 32% and 5.45% than the speed of a network approach using traditional adders and multipliers and the speed of the basic dot product architecture, respectively.

A multi-path fused add-subtract unit for Digital Signal Processing

The task of computing both the summation and difference of a pair of Floating-Point (FP) data is often needed in some Digital Signal Processing (DSP) algorithms and other applications. A basic fused add-subtract unit (FAS) is introduced [1] to perform simultaneously both addition and subtraction operation for a couple of operands and has less hardware overhead than the general approach using two FP adders. In this paper, a novel multi-path FAS unit is presented to accelerate the basic FAS architecture. The implementation results in FP single precision data format show that the multi-path FAS is 48.7% faster and 16.9% smaller than the basic FAS unit.

Research of the High-Speed Fibre Switch Network NIC Based on the Memory Communication

At present, the FC NIC (the Fiber Channel Network Interface Card) is mostly based on traditional I/O bus, such as PCI, and is viewed as peripheral equipment, the communication data is copied between the NIC and the computer memory when communicating. Then, its communication delay is long, and its communication performance is limited by the corresponding I / O bus. So, in this paper, the Direct Memory Communication method, abbreviated as DMC, is forwarded to apply in the high-speed fiber switch network. The FC NIC based on DMC, noted as FC-DMC NIC, has the same slot as the memory, and is inserted into one memory slot, the memory on FC-DMC NIC is considered as the computer ordinary memory, and reserved as Communication Precinct. When user sends data, he uses the method of writing memory to place the data into communication space, and when user receives data, he uses the method of reading memory to get the data from communication space. So, the user can accomplished the direct point-to-point communications between two computers through accessing memory. The communications speed of FC-DMC NIC isn’t limited by I/O bus, and the data copy between the memory and the NIC is omitted. Experiments show that DMC is right and FC-DMC NIC has better communication performance.

Study on L2 cache of multi-core processor and optimization for embedded

L2 cache is an important part of the modern microprocessor architecture. The emergence and application of multi-core processors puts forward higher and more complex requirements for cache architecture design. Meanwhile, the multi-core processors begin to appear in embedded fields, which have special requirements. Therefore, designing high-efficiency L2 cache structure becomes one of the key technologies in multi-core processors designs, especially in embedded fields. Based on the multi-core processors OpenSPARC T1, this paper analysed the structures and functions of L2 cache, then studied the implementation of relevant source codes. In order to adapt embedded needs, on the basis of modifying source codes, this paper conducted some simulations to discuss how buffer-size parameters could influence the performance of L2 cache. According to the conclusions and embedded applications, the paper made certain optimization of the buffers in L2 cache for embedded.

Designing a Twinax communication circuit

This paper describes the design and FPGA implementation of a Twinax communication circuit. It is designed to interface with IBMs local Twinax protocol, and is hardware compatible with IBM Enhanced 5250 Emulation Adapter Card. This circuit is composed of a processor interface unit and two Channel Control Modules (CCM). This paper presents an implementation of a Twinax Communication Adapter Chip with FPGA (Field Programmable Gate Array). It is organized into three parts: (1) introduction; (2) functional overview; and (3) logic design and implementation.