Gao Deyuan

A high-resolution multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications

This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay-locked loops is proposed for fine conversion. The resolution range is achieved from 71 ps to 142 ps by use of a reference clock from 100 MHz to 50 MHz. The measured range of the TDC is 10 µs. A prototype chip of 3-channel TDC for PET imaging system is designed and fabricated in AMS 0.35 µm CMOS technology. The area of the chip is 8.4 mm2 in size. The differential nonlinearity is ±0.1 LSB. The integral nonlinearity is ±0.1 LSB. The circuits will be extended to 64 channels for small animal PET imaging system.

Dual-path architecture of floating-point dot product computation

Dot product computation is widely used in many algorithms, such as FFT and DCT. This paper proposes a floating-point dot product architecture based on the multiple-path method. This architecture could perform A × B+C × D as a single operation. The speed of the dual-path architecture implemented in single precision format is faster by 32% and 5.45% than the speed of a network approach using traditional adders and multipliers and the speed of the basic dot product architecture, respectively.

A multi-path fused add-subtract unit for Digital Signal Processing

The task of computing both the summation and difference of a pair of Floating-Point (FP) data is often needed in some Digital Signal Processing (DSP) algorithms and other applications. A basic fused add-subtract unit (FAS) is introduced [1] to perform simultaneously both addition and subtraction operation for a couple of operands and has less hardware overhead than the general approach using two FP adders. In this paper, a novel multi-path FAS unit is presented to accelerate the basic FAS architecture. The implementation results in FP single precision data format show that the multi-path FAS is 48.7% faster and 16.9% smaller than the basic FAS unit.

A novel concurrent error detection circuit for Leading Zero Anticipator

Leading Zero Anticipator (LZA) is a technique to calculate the number of leading zeros of the result in parallel with the addition. General algorithms can work effectively for a subtraction, and obtain the leading one position from exponents of operands for an addition or a multiply-add-fused (MAF) operation. However, using exponents to get leading zero number can introduce another error of one bit because of a carry into the leading one position. Moreover, when taking denormalized operands into account, the leading one position does not relate with exponents anymore. This paper presents a novel concurrent error detection circuit for an exact LZA which can work effectively for both addition and subtraction. In addition, a simpler pre-encoding method is employed to reduce the hardware complexity of the concurrent error detection circuit. The total area of the proposed LZA is reduced by 7.5% compared with that of a generalLZA.

Study on high performance bus interface of RISC microprocessor

The performance gap caused by higher clock rate of processor and lower of DRAM is severe, and the memory system becomes one of the primary bottlenecks. Further, within the memory system, the memory bus accounts for a substantial portion of the primary memorys overhead. Some approaches are studied in this paper to improve the performance of the microprocessor bus interface, including out-of-order, pipelined and split-bus transaction, load/store buffer model and the design of asynchronous interface. These methods are used in the design of ARS03 microprocessor that we developed to implement an efficient processor bus interface, to facilitate access to main memory and other bus subsystems. The simulation results of real programs show that the penalties of long memory latencies are mitigated. The execution cycles are reduced at a rate 9.1% to 36.7%.The performance gap caused by higher clock rate of processor and lower of DRAM is severe, and the memory system becomes one of the primary bottlenecks. Further, within the memory system, the memory bus accounts for a substantial portion of the primary memorys overhead. Some approaches are studied in this paper to improve the performance of the microprocessor bus interface, including out-of-order, pipelined and split-bus transaction, load/store buffer model and the design of asynchronous interface. These methods are used in the design of ARS03 microprocessor that we developed to implement an efficient processor bus interface, to facilitate access to main memory and other bus subsystems. The simulation results of real programs show that the penalties of long memory latencies are mitigated. The execution cycles are reduced at a rate 9.1% to 36.7%.

An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC–DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pumps power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.

A Modified ecimation ilter esign for Oversampled Sigma elta A/ Converters

The paper presents a novel lower power polyphase transformable stage nonrecursive comb (PTSNC) filter architecture considering the area and power consumption, which is very suitable for high-order oversampled sigma delta A/D converters. The proposed decimation filter has 1/3 less hardware and power compared to conventional non-recursive decimation filters when the filter was implemented using 0.6-mum CMOS standard when the circuit work clock was 100MHz

Designing a Twinax communication circuit

This paper describes the design and FPGA implementation of a Twinax communication circuit. It is designed to interface with IBMs local Twinax protocol, and is hardware compatible with IBM Enhanced 5250 Emulation Adapter Card. This circuit is composed of a processor interface unit and two Channel Control Modules (CCM). This paper presents an implementation of a Twinax Communication Adapter Chip with FPGA (Field Programmable Gate Array). It is organized into three parts: (1) introduction; (2) functional overview; and (3) logic design and implementation.

Developing plug and play 5250-TA chip with FPGA

The emerging PnP is expected to become popular within nearly few years. This paper redesigned an ASIC by integrating in a PnP part for tomorrows markets, and prototyped the PnP ASIC with FPGA. The PnP protocol and its design within an ASIC is presented.

The design of PCM tester using FPGA

The PCM tester receives external data from RS-422 bus or ARMC429 bus, processes it and passes it to the memory of a personal computer according to the required format. This paper describes the function and architecture of the PCM tester in detail, and gives an approach to implement it by Xilinx FPGA. Besides, author draws some conclusions about bow to make good use of the feature of FPGA to improve a design.