Fangming Ye

TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation

Three-dimensional integration based on die/wafer stacking and through-silicon-vias (TSVs) promises to overcome interconnect bottlenecks for nanoscale integrated circuits (ICs). However, TSVs are prone to defects such as shorts and opens that affect circuit operation in stacked ICs. We analyze the impact of open defects on TSVs and describe techniques for screening such defects. The proposed characterization technique estimates the additional delay introduced due to a resistive open defect as well as due to rerouting based on spare TSVs. We also present an optimization method based on integer linear programming (ILP) that allocates spares to functional TSVs such that the spare for a functional TSV is neither too close to a functional TSV (to avoid the case of both functional and spare TSV being defective) nor too far to ensure that the additional delay due to rerouting is below an upper limit. Results are presented using Hspice simulations based on a 45 nm predictive technology model, recently published data on TSV parasitics, and a commercial ILP solver.

TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) have emerged as a promising solution for overcoming interconnect and power bottlenecks in IC design. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3D integration commercially viable. This paper first presents an overview of TSV-related defects and the impact of TSVs in the form of new defects in devices and interconnects. The paper next describes recent advances in testing, diagnosis, and design-for-testability for 3D ICs and techniques for defect tolerance using redundancy and repair. Topics covered include various types of TSV defects, stress-induced mobility and threshold-voltage variation in devices, stress-induced electromigration in inter-connects, pre-bond and test-bond testing (including TSV probing), and optimization techniques for defect tolerance.

Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting

Increasing integration densities and high operating speeds lead to subtle manifestation of defects at the board level. Functional fault diagnosis is, therefore, necessary for board-level product qualification. However, ambiguous diagnosis results lead to long debug times and even wrong repair actions, which significantly increase repair cost and adversely impact yield. Advanced machine-learning (ML) techniques offer an unprecedented opportunity to increase the accuracy of board-level functional diagnosis and reduce high-volume manufacturing cost through successful repair. We propose a smart diagnosis method based on two ML classification models, namely, artificial neural networks (ANNs) and support-vector machines (SVMs) that can learn from repair history and accurately localize the root cause of a failure. Fine-grained fault syndromes extracted from failure logs and corresponding repair actions are used to train the classification models. We also propose a decision machine based on weighted-majority voting, which combines the benefits of ANNs and SVMs. Three complex boards from the industry, currently in volume production, and additional synthetic data, are used to validate the proposed methods in terms of diagnostic accuracy, resolution, and quantifiable improvement over current diagnostic software.

On effective and efficient in-field TSV repair for stacked 3D ICs

Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption. However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms. In particular, thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing errors on critical paths with TSVs, thereby resulting in accelerated chip failure in the field. Burn-in for screening latent defects during manufacturing is expensive and its effectiveness for new TSV defect types has yet to be thoroughly characterized. We describe a reconfigurable in-field repair solution that is able to effectively tolerate latent TSV defects through the judicious use of spares. The proposed solution includes a reconfigurable repair architecture that enables spare TSV sharing between TSV grids, and the corresponding in-field repair algorithms. The effectiveness and efficiency of our proposed solution is evaluated using 3D benchmark designs.

Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees

Functional fault diagnosis at board-level is desirable for high-volume production since it improves product yield. However, to ensure diagnosis accuracy and effective board repair, a large number of syndromes must be used. Therefore, the diagnosis cost can be prohibitively high due to the increase in diagnosis time and the complexity of syndrome collection/analysis. We propose an adaptive diagnosis method based on decision trees (DTs). Faulty components are classified according to the discriminative ability of the syndromes in DT training. The diagnosis procedure is constructed as a binary tree, with the most discriminative syndrome as the root and final repair suggestions are available as the leaf nodes of the tree. The syndrome to be collected in the next step is determined based on the observations of syndromes collected thus far in the diagnosis procedure. The number of syndromes required for diagnosis can also be significantly reduced compared to the number of syndromes used for system training. Diagnosis results for two complex boards from industry, currently in volume production, and additional synthetic data highlight the effectiveness of the proposed approach.

Representative critical-path selection for aging-induced delay monitoring

Transistor aging degrades path delay over time and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential and to respond to this need, several delay sensor designs have been proposed in the literature. However, due to the significant overhead of these designs and the large number of critical paths in todays IC, it is infeasible to monitor the delay of every critical path in silicon. We present an aging-aware representative path-selection method that allows us to measure the delay of a small set of paths and infer the delay of a larger pool of paths that are likely to fail due to transistor aging. Moreover, since aging is affected by process variations and runtime variations in temperature and voltage, we use machine learning and linear algebra to incorporate these variations during representative path selection. Simulation results for benchmark circuits highlight the accuracy of the proposed approach for predicting critical path delay based on the selected representative paths.

Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning

Advanced machine learning techniques offer an unprecedented opportunity to increase the accuracy of board-level functional fault diagnosis and reduce product cost through successful repair. Ambiguous or incorrect diagnosis results lead to long debug times and even wrong repair actions, which significantly increase repair cost. We propose a smart diagnosis method based on multikernel support vector machines (MK-SVMs) and incremental learning. The MK-SVM method leverages a linear combination of single kernels to achieve accurate faulty-component classification based on the errors observed. The MK-SVMs thus generated can also be updated based on incremental learning, which allows the diagnosis system to quickly adapt to new error observations and provide even more accurate fault diagnosis. Two complex boards from industry, currently in volume production, are used to validate the proposed diagnosis approach in terms of diagnosis accuracy (success rate) and quantifiable improvements over previously proposed machine-learning methods based on several single-kernel SVMs and artificial neural networks.

Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines

Advanced machine learning techniques offer an unprecedented opportunity to increase the accuracy of board-level functional fault diagnosis based on the historical data of successfully repaired boards. However, the training complexity increases significantly in diagnosis systems due to the increasing amount of the historical data. We propose a smart learning method in the diagnosis system using incremental support-vector machines (SVMs). The SVMs updated using incremental learning allow the diagnosis system to quickly adapt to new error observations and provide more accurate fault diagnosis. Two sets of large-scale synthetic data generated from the log information of two complex industrial boards, in volume production, are used to validate the proposed diagnosis approach in terms of training time and diagnosis accuracy over a previously proposed diagnosis system based on simple support-vector machines.

Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis

High-volume manufacturing of complex electronic products involves functional test at board level to ensure low defect escapes. Machine-learning techniques have recently been proposed for reasoning-based functional-fault diagnosis system to achieve high diagnosis accuracy. However, machine learning requires a rich set of test items (syndromes) and a sizable database of faulty boards. An insufficient number of failed boards, ambiguous root-cause identification, and redundant or irrelevant syndromes can render machine learning ineffective. We propose an evaluation and enhancement framework based on information theory for guiding diagnosis systems using syndrome and root-cause analysis. Syndrome analysis based on subset selection provides a representative set of syndromes with minimum redundancy and maximum relevance. Root-cause analysis measures the discriminative ability of differentiating a given root cause from others. The metrics obtained from the proposed framework can also provide guidelines for test redesign to enhance diagnosis. A real board from industry, currently in volume production, and an additional synthetic board, based on data extrapolated from another real board, are used to demonstrate the effectiveness of the proposed framework.

Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection

Process together with runtime variations in temperature and voltage, as well as transistor aging, degrade path delay and may eventually induce circuit failure due to timing variations. Therefore, in-field tracking of path delays is essential, and to respond to this need, several delay sensor designs have been proposed in the literature. However, due to the significant overhead of these sensors and the large number of critical paths in todays IC, it is infeasible to monitor the delay of every critical path in silicon. We present an aging- and variationaware representative path selection technique based on machine learning that allows to measure the delay of a small set of paths and infer the delay of a larger pool of paths that are likely to fail due to delay variations. Simulation results for benchmark circuits highlight the accuracy of the proposed approach for predicting critical-path delay based on the selected representative paths.