K. De Meyer

Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. TSV resistance, inductance, and capacitance need to be modeled to determine their impact on the performance of a 3-D circuit. In this paper, the RLC parameters of the TSV are modeled as a function of physical parameters and material characteristics. Models are validated with the numerical simulators like Raphael and Sdevice and with experimental measurements. The TSV RLC model is applied to predict the resistance, inductance, and capacitances of small-geometry TSV architectures. Finally, this paper also proposes a simplified lumped TSV model that can be used to simulate 3-D circuits.

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.

VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices

Low-voltage low-power nonvolatile floating-gate memory device operation can be achieved by using alternative tunnel barriers consisting of at least two dielectric layers with different dielectric constants k. Low-k/high-k (asymmetric) and low-k/high-k/low-k (symmetric) barriers enable steeper tunneling current-voltage characteristics. Their implementation is possible with high-k dielectric materials that are currently investigated for SiO/sub 2/ replacement in sub-100-nm CMOS technologies. We show that a reduction in programming voltages of up to 50% can be achieved. This would significantly reduce the circuitry required to generate the high voltages on a nonvolatile memory chip, while maintaining sufficient performance and reliability.

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

Germanium is a widely used material for tunnel FETs because of its small band gap and compatibility with silicon. Typically, only the indirect band gap of Ge at 0.66 eV is considered. However, direct band-to-band tunneling (BTBT) in Ge should be included in tunnel FET modeling and simulations since the energy difference between the Ge conduction band edges at the L and Γ valleys is only 0.14 eV at room temperature. In this paper, we theoretically calculate the parameters A and B of Kanes direct and indirect BTBT models at different tunneling directions ([100], [110], and [111]) for Si, Ge and unstrained Si1-xGex. We highlight how the direct BTBT component becomes more important as the Ge mole fraction increases. The calculation of the band-to-band generation rate in the uniform electric field limit reveals that direct tunneling always dominates over indirect tunneling in Ge. The impact of the direct transition in Ge on the performance of two realistic tunnel field-effect transistor configurations is illustrated with TCAD simulations. The influence of field-induced quantum confinement is included in the analysis based on a back-of-the-envelope calculation.

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFETs with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Impact ionization in silicon: A review and update

Abstract After defining the multiplication factor and the ionization rate together with their interrelationship, multiplication and breakdown models for diodes and MOS transistors are discussed. Different ionization models are compared and test structures are discussed for measuring the multiplication factor accurately enough for reliable extraction of the ionization rates. Multiplication measurements at different temperatures are performed on a bipolar NPN transistor, and yield new electron ionization rates at relatively low electrical fields. An explanation for the spread of the experimental values of the existing data on ionization rate is given. A new implementation method for a local avalanche model into a device simulator is presented. The results are less sensitive to the chosen grid size than the ones obtained from the existing method.

Impact of Line-Edge Roughness on FinFET Matching Performance

As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact of LER on the matching performance of FinFETs is investigated through statistical device simulations, comparing the relative importance of fin- and gate-LER. Fin-LER is shown to significantly degrade FinFET matching performance under DC and transient operations. Combining our device simulation results with experimental data, it is shown that fin-LER will dominate the intra-bit-cell stochastic mismatch in FinFET static random access memories at the LSTP-32-nm node. The electrical performance of spacer-defined fin (SDF) and resist-defined fin (RDF) patterning technologies has been compared. It is shown that, with respect to RDF patterning, the spacer-defined process has the potential to improve FinFET matching performance by 90%.

Passivation of Ge ( 100 ) ∕ GeO2 ∕ high-κ Gate Stacks Using Thermal Oxide Treatments

The physical and electrical properties of Ge/GeO 2 /high-κ gate stacks, where the GeO 2 interlayer is thermally grown in molecular oxygen, are investigated. The high-K layer (ZrO 2 , HfO 2 , or Al 2 O 3 ) is deposited in situ on the GeO 2 interlayer by atomic layer deposition. Detailed analysis of the capacitance-voltage and conductance-frequency characteristics of these devices provides evidence for the efficient passivation of the Ge(100) surface by its thermal oxide layer. A larger flatband voltage hysteresis is observed in HfO 2 -based gate stacks, as compared to Al 2 O 3 gate stacks, which is possibly related to the more pronounced intermixing observed between the HfO 2 and GeO 2 .

Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.

Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance

Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Among the sources of variability, line-edge-roughness (LER) and random dopant (RD) fluctuations are significant in current technology nodes. In this paper, the impact of the LER and RD on the matching performance of FinFETs is investigated for the LSTP-32 nm node, where these devices represent an attractive alternative to the planar CMOS transistors. Line-edge-roughness contributions from the fin, top-, and side wall-gates of n- and p-channel FinFETs are compared by means of 2-D and 3-D technology computer-aided design (TCAD) simulations, performed with a quantum-corrected hydrodynamic model on large statistical ensembles. Correlations between geometrical roughness and resulting electrical parameters are analyzed to provide further insight into the impact of the LER. A noise analysis approach is adopted to evaluate the impact of RD fluctuations throughout the impurity concentration ranges of interest, providing a direct comparison with the line-edge-roughness contributions. The impact of the extension doping profile specifications on the LER- and RD-induced mismatch is investigated, highlighting the potential drawbacks of junction engineering.