Farbod Behbahani

CMOS mixers and polyphase filters for large image rejection

This paper presents an in-depth treatment of mixers and polyphase filters, and how they are used in rejecting the image in transmitters and receivers. A powerful phasor-based analysis is used to explain all common image-reject topologies and their limitations, and it is shown how this can replace complex trigonometric equations commonly found in the literature. Practical problems in design and layout that limit the performance of image-reject upconversion and downconversion mixers are identified, and solutions are presented or limits explained. This understanding is put to work in a low-IF CMOS wideband, low-IF downconversion circuit, which repeatedly rejects the image by 60 dB over the wide band of 3.5 to 20 MHz without trimming or calibration.

A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver

Researchers agree that the active filter for channel-selection limits the dynamic range in a fully integrated wireless receiver, which uses no external components. This paper describes a filter designed for a wideband wireless LAN receiver operating in the 2.4-2.48 GHz ISM band. The receiver converts the desired channel to a low IF to enable on-chip rejection of the image. The analog filter must pass up to a 10 MHz wide single-channel centered after downconversion to IF ranging from 5 to 10 MHz. The classic requirements on all RF ICs apply to this filter, namely how to achieve the desired frequency response with the highest linearity and lowest noise at a given current consumption. For a channel-select filter, linearity is specified as out-of-band 3rd order intercept (IP3), to limit the in-band intermodulation from large interferers lying in the filter stop band. This work addresses the problem in filter architecture and circuit implementation. The achieved dynamic range surpasses all other published filter designs, except those cases where gain is favorably interleaved with filtering.

A 2.4-GHz low-IF receiver for wideband WLAN in 6-/spl mu/m CMOS-architecture and front-end

This paper presents the 2.4-GHz front-end and the first downconversion section of a fully integrated low-IF receiver. The dual-conversion receiver rejects the image repeatably by 60 dB using integrated polyphase filters without calibration or tuning. The gain of the RF mixer and IF amplifier is switchable to slide the available dynamic range of the following stages based on the conditions of the input signal. The front-end and downconversion sections drain 35 mA on average from a 3.3-V supply. Minimum cascade noise figure is 7.2 dB, and maximum cascade IIP3 is -3.4 dBm.

A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection

A fully integrated Global Positioning System (GPS) radio is presented. Low-IF architecture was used for a high level of integration and low power consumption. An on-chip analog image-reject filter provides 18 dB of image-noise rejection to prevent noise figure (NF) degradation. With image rejection performed in the analog radio, a single-path (nonquadrature) output was used. The integrated synthesizer only requires an off-chip phase-locked loop-filter to function. Implemented in a 0.35-/spl mu/m 2P4M CMOS process, the integrated radio has a chip area of 9.5 mm/sup 2/. The radio operates over a wide range of voltage and temperature, from 2.2 to 3.6 V and from -40/spl deg/C to +85/spl deg/C and consumes 27 mW from a 2.2-V supply. The receiver has 4 dB NF.

Adaptive analog IF signal processor for a wide-band CMOS wireless receiver

An IF strip for a wireless receiver supports a variable baud rate by changing analog filter bandwidth. Sliding and step adaptive dynamic range are both used at IF to dissipate only the necessary power at prevailing channel conditions. A combination of VGA and PGA is developed for 64-QAM. The total signal processor draws an average of 16 mA from 3.3 V and a peak of 73 mA. The differential input noise is as low as 3.9 nV//spl radic/Hz, while maximum IIP3 is +22 dBm with respect to 100 ohms.

Level-locked loop: a technique for broadband quadrature signal generation

A method for precise wideband quadrature signal generation is presented. A divide-by-2 stage forms an adjustable phase quadrature signal generator. Its output phase error is converted to an error signal, which feeds back to the quadrature signal generator through an integrator, to correct the output phase difference. Using this method, a phase accuracy better than 0.5/spl deg/ is achieved over 40 MHz to 500 MHz of output frequency without any external tuning. The loop compensates for any circuit and layout mismatches, is not sensitive to distorted input LO signals, and has no inherent high frequency limitation.

CMOS 10 MHz-IF downconverter with on-chip broadband circuit for large image-suppression

A highly selective superheterodyne radio receiver has so far defied complete integration because it is difficult to adequately reject the image with only on-chip circuits. Practical quadrature downconversion mixers, limited by gain mismatch and phase inaccuracy, usually reject the image by no more than 35 dB or so. This may be good enough in a low intermediate frequency (IF) receiver for certain cellular systems such as GSM or DECT, because the base station limits the relative power of the adjacent channels comprising the image. However, in non-cellular or unregulated ISM bands the adjacent channel level, and therefore the strength of the image, is relatively unconstrained. This paper describes a circuit that rejects the image by almost 60 dB over two octaves of frequency centered at 10 MHz with no need for adjustment or tuning. It is intended for use in a fully integrated low-IF superheterodyne receiver. The prototype circuit is implemented in 0.6 /spl mu/m CMOS.

A low distortion bipolar mixer for low voltage direct up-conversion and high IF systems

This paper describes the implementation of a low distortion mixer for direct up-conversion and high IF systems. A Gilbert cell with a low distortion transconductance constitutes the mixer core. A current feedback loop is used to linearize the transconductance stage, achieving an alternate channel leakage of -71 dBc with a power penalty of 15%. The mixer operates from 2.7 to 7.5 V of supply voltage and over a temperature range of -40 to 85/spl deg/C. It provides -3 dBm output power while drawing 7.5 mW from a 3-V supply. The mixer is implemented in 1-/spl mu/m BiCMOS for a global system for mobile communications (GSM) chip set.

An adaptive 2.4 GHz low-IF receiver in 0.6 /spl mu/m CMOS for wideband wireless LAN

High bit-rate communications require wideband channels and complex modulation schemes, such as QAM, to convey multiple bits per symbol. Available bandwidth (BW) and desired user density per cell together determine the BW allocated per channel. In short-range applications like indoor wireless LAN where transmitted power is limited to 1 mW, FCC rules allow channel BW higher than 1 MHz. This system adapts to channel bandwidths ranging from 0.625 MHz to 10 MHz, and modulations spanning 4-QAM to 64-QAM. The carrier frequency is slowly hopped across the 2.4 GHz ISM band.

A 27 mW GPS radio in 0.35 /spl mu/m CMOS

A pure-CMOS 1.575 GHz radio integrates a receiver and a synthesizer for GPS application. The receiver path uses a quadrature single-downconversion architecture with an on-chip image reject LPF. It has 4 dB NF and -17 dBm IIP3 and operates over 2.2 V to 3.6 V supply and -40 to 85/spl deg/C. It consumes 27 mW from 2.2 V supply.