Mohammad Nariman

A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier

The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die.

A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection

A fully integrated Global Positioning System (GPS) radio is presented. Low-IF architecture was used for a high level of integration and low power consumption. An on-chip analog image-reject filter provides 18 dB of image-noise rejection to prevent noise figure (NF) degradation. With image rejection performed in the analog radio, a single-path (nonquadrature) output was used. The integrated synthesizer only requires an off-chip phase-locked loop-filter to function. Implemented in a 0.35-/spl mu/m 2P4M CMOS process, the integrated radio has a chip area of 9.5 mm/sup 2/. The radio operates over a wide range of voltage and temperature, from 2.2 to 3.6 V and from -40/spl deg/C to +85/spl deg/C and consumes 27 mW from a 2.2-V supply. The receiver has 4 dB NF.

A 2.1mW/3.2mW delay-compensated GSM/WCDMA ΣΔ analog-digital converter

A technique to compensate for the harmful excess loop delay in a continuous time SigmaDelta analog-digital converter is presented. With no extra power consumption or area penalty the technique is suitable for variety of applications employing continuous time SigmaDelta analog-digital converters. This work presents a dual mode SigmaDelta ADC for GSM/WCDMA applications with DR of 86 dB/63 dB for 100 KHz/1.92 MHz in a 65 nm CMOS technology with power consumption of 2.1 mW/3.2 mW.

A quad-band GSM/GPRS/EDGE SoC in 65nm CMOS

A quad-band 2.5G SoC integrates all the RF, DSP, ARM, audio and other baseband processing functions into a single 65nm CMOS die. The radio draws a battery current of 49mA in the RX-mode, and 86mA in the GMSK TX-mode. The low-IF receiver achieves a sensitivity of −110dBm at the antenna, corresponding to a noise figure of 2.4dB at the device input. The 8PSK ±400kHz modulation mask is −64.1/62.7dBc for high/low bands, with an RMS EVM of 2.45/1.95%.

A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS

A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on the radio portion mostly, and addresses the challenges of realizing a complete GSM/EDGE SoC with the RF integrated along with the rest of digital baseband circuitry. Several circuit level as well as architectural techniques are presented to realize a very low-cost and low-power 2.5G radio while meeting the stringent cellular requirements with wide margin. The radio draws a battery current of 49 mA in the receiver-mode, and 86/77 mA in the GMSK/8PSK transmit-mode. The low-IF receiver achieves a sensitivity of -110 dBm at the antenna, corresponding to a noise figure of 2.4 dB at the device input. The 8PSK±400 kHz modulation mask is - 64.1/62.7 dBc for high/low bands, with an RMS EVM of 2.45/1.95%. The radio core area is 3.95 mm2 .

A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS

This radio integrates all the receive and transmit functions required to support a quad-band GSM/GPRS/EDGE application into a single CMOS chip. Compared to the published work, this transceiver is implemented in low-cost digital 0.13 mum CMOS, achieves a superior receive and transmit performance, and yet has up to 2x lower receive power consumption, a key requirement in cellular applications.

A 27 mW GPS radio in 0.35 /spl mu/m CMOS

A pure-CMOS 1.575 GHz radio integrates a receiver and a synthesizer for GPS application. The receiver path uses a quadrature single-downconversion architecture with an on-chip image reject LPF. It has 4 dB NF and -17 dBm IIP3 and operates over 2.2 V to 3.6 V supply and -40 to 85/spl deg/C. It consumes 27 mW from 2.2 V supply.

Transmitter development for cellular integrated circuits

This article reviews transmitter topologies for radio transceivers with emphasis on cellular applications. In the first section it discusses different architectures and the challenges in practical implementations. Then it presents a transmitter as part of a fully integrated transceiver for GSM/GPRS/EDGE.