Farid Sebaai

Wet Selective SiGe Etch to Enable Ge Nanowire Formation

For the Ge nanowire formation in a gate-all-around (GAA) integration scheme, a selective etch of Si0.5Ge0.5 or Si0.3Ge0.7 selective to Ge is considered. Two wet process approaches were evaluated: a boiling TMAH as a commodity chemistry is compared with a formulated chemistry using a multi-stack SiGe/Ge layer as a test vehicle. The boiling TMAH exhibits an anisotropic etch of the SiGe whereas the formulated semi-aqueous chemistry removes the sacrificial SiGe by an isotropic etch which makes the process suitable for a Ge nanowire release process.

Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme

With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].

First Demonstration of SiGe Channel in Macaroni Geometry for Future 3D NAND

We demonstrate for the first time a 20% [Ge] SiGe Macaroni channel in 3D NAND. Two alternative integration routes have been explored and High Pressure Annealing Process in D2 ambient has been applied to improve the channel and the channel-SiO2 interface. Electrical performance indicates that SiGe can improve channel conduction, with minimal impact on memory performance, but has intrinsically worse off-current properties than Si.

Effect of Dissolved Oxygen for Advanced Wet Processing

of these new materials have necessitated the evaluation of new chemicals and processing methods. The control of the Dissolved Oxygen (DO) concentration to suppress Cu corrosion is well established in BEOL processing and likewise in order to achieve a hydrophobic surface after pre-epi cleaning in FEOL surface preparation [2].

Poly-Silicon Wet Removal for Replacement Gate Integration Scheme: Impact of Process Parameters on the Removal Rate

We report in this work some process optimization effort in performing poly silicon removal for replacement gate process integration. Successful wet poly silicon removal after dummy gate patterning is not only conditioned by suitable process conditions during wet removal but is also impacted by process steps prior to gate removal A thorough evaluation of the impact on poly removal from dopants or contaminants introduced in the poly silicon by previous processing is done, resulting in an optimized integration flow with successful poly removal. This work also shows that use of diluted TMAH chemistry instead of diluted ammonia in performing poly silicon removal provides better ability in removing poly silicon especially in narrow gate structures.

Wet Etching Behavior of Poly-Si in TMAH Solution

Since Tetramethylammonium Hydroxide (TMAH) became widely used as a silicon etchant, e.g. the dummy gate removal for gate-last approach (RMG) [1, or Si fin formation on FinFET [, some careful preparations and optimizations have required implementation. These adaptations have involved not only chemical-related issues, but also hardware-related in order to satisfy the necessary process performance.

Cleaning of High Aspect Ratio STI Structures for Advanced Logic Devices by Implementation of a Surface Modification Drying Technique

The continuous down scaling of the dimensions for the logic devices has imposed to carefully track the pattern collapse issue when cleaning after FIN etch. Showing the limitations of the hot IPA drying technique toward scaled FIN dimensions, a cleaning using a surface modification drying technique has been proposed and successfully implemented. It is also discussed the use of some post treatment solutions to remove the grafted layer used to modify the FIN surface while preserving the integrity of the FIN structures.

300 mm Wafer Development for Pattern Collapse Evaluations

Over the past decade, many advanced drying techniques have been developed to reduce and prevent pattern collapse of high aspect ratio (HAR) structures after wet processing. However, different dimensions, profiles and materials of HAR structures used in literature make it difficult to compare the efficiency of different drying processes. In this work, standard 300 mm wafer test structures, characterization and analysis techniques have been developed for quantitative analysis of pattern collapse rate as a function of the intrinsic mechanical property of HAR structures. Such standardized single wafer evaluations are important for benchmarking different drying techniques.

SiGe vs. Si Selective Wet Etching for Si Gate-all-Around

Gate All-Around (GAA) is considered a key design feature for future CMOS technology. SiGe vs. Si selective etch is required for Si nanowire formation in GAA. It is confirmed the selective SiGe removal with commodity chemical (mixtures of hydrofluoric acid (HF), hydrogen peroxide (H2O2) and acetic acid (CH3COOH, HAc)), however the thick oxidized layer on Si NW was observed after commodity chemical process, which is indicated the significant Si NW loss. On the other hand, the formulated mixture ACT® SG-101, which is focusing on SiGe oxidizer, chemical pH, solvent polarity & corrosion inhibitor for chemical concept, was performed higher selectivity and lower Si loss than commodity chemical. The formulated mixture has also been used to form an inner spacer for cavity etch scheme and confirmed uniform cavity etch and inner spacer filling on topological test structure.

Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs

A selective wet etching process for fabricating SiGe and Ge nanowires for gate all around transistors is introduced in this paper. Two formulated proprietary chemical mixtures with highly selective etching properties (Si vs. SiGe and SiGe vs. Ge) can effectively dissolve the sacrificial layers with minimal damage to the interstitial nanowire materials. The Auger Electron Spectroscopy (AES) surface characterization indicates that no chemical contamination is left after the wet etching process.