K. Devriendt

A new complementary hetero-junction vertical Tunnel-FET integration scheme

This paper presents a new integration scheme for complementary hetero-junction vertical Tunnel FETs (VTFETs), whereby a sacrificial source layer is used during the device fabrication and replaced by the final hetero-source materials, respectively for n- or p-TFETs, thereby minimizing the thermal budget applied to the source junctions. With the demonstration of this source-replacement-last module for a vertical Ge hetero-junction n-TFET, we show that it is possible to grow highly doped hetero-junctions on a Si channel with steep doping profiles and without damaging the high-κ gate-dielectric interface. This scheme allows for the integration of complementary low-bandgap materials on a Si platform providing high on-currents combined with the Si channel based low off-currents.

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

We have fabricated fully Ni-silicided metal gate (FUSI) CMOS devices with HfO2-based gate dielectrics for the first time. We demonstrate that full silicidation eliminates the Fermi level pinning at the polySi-HfO2 dielectric interface in pFETs. For nMOS devices, a 5 orders of magnitude reduction in short channel sub-threshold leakage is obtained with similar drive current compared to the poly gate devices. In addition, the FUSI process does not degrade the hysterisis nor the dielectric breakdown. This result makes FUSI on high-K a strong candidate for scaled low power technologies.

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

Flexibly controllable threshold-voltage (V_th) asymmetric gate-oxide thickness (T_ox) four-terminal (4T) FinFETs with HfO₂ [equivalentoxidethickness(EOT)=1.4 nm] for the drive gate and HfO₂+thick SiO₂ (EOT=6.4-9.4 nm) for the V_th-control gate have been successfully fabricated by utilizing ion-bombardment-enhanced etching process. Owing to the slightly thick V_th-control gate oxide, the subthreshold slope (S) is significantly improved as compared to the symmetrically thin T_ox 4T-FinFETs. As a result, the asymmetric T_ox 4T-FinFETs gain higher I_on than that for the symmetrically thin T_ox 4T-FinFETs under the same I_off conditions

Work function engineering by FUSI and its impact on the performance and reliability of oxynitride and Hf-silicate based MOSFETs

In this work, we report an extensive characterisation of fully silicided gate (FUSI) devices with oxynitride (SiON) and Hf-silicate gate dielectrics. Enhanced drive current is obtained, in comparison with poly gate devices, together with an increase in electron/hole mobility and reduction in CET values. We show that the work function (WF) can be engineered by doping of the poly gates prior to FUSI for SiON devices but not for Hf-silicate devices. With reference to the poly gate, Hf-silicate/FUSI devices exhibit improved TDDB reliability behavior, having higher acceleration factor (/spl gamma/) values. NBTI gives a maximum operating voltage above 1.2 V for /spl Delta/V/sub T/ = 10% or 30 mV, as extrapolated for a 10 years-lifetime.

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

Ge-Source Vertical Tunnel FETs Using a Novel Replacement-Source Integration Scheme

The Ge-source tunnel FETs (TFETs) are fabricated using a novel replacement-source approach, whereby a dummy source is replaced at the end of the process flow by the final source material to form an heterojunction. We show that the source can be successfully replaced while maintaining the gate dielectric integrity in the gate-source overlap (GS-OL) region and selectively to the exposed materials. Due to the in situ-doped epitaxial-grown source and the low thermal budget, this integration scheme leads to the formation of a highly doped source and an abrupt tunnel heterojunction and allows the integration of complementary devices. Electrical characterization of the devices shows performance improvement over their SiGe-source heterojunction and Si homojunction vertical TFET counterparts. Temperature dependence indicates that the subthreshold region of the devices is degraded due to trap-assisted tunneling (TAT). Band-to-band tunneling (BTBT) contribution is, however, revealed at low temperature (78 K) with a minimum point slope of ~50 mV/decade. The impact on performance of different device parameters is assessed. The amount of GS-OL or crystalline Ge (c-Ge) thickness in the source does not affect the device characteristics owing to the fact that the devices are dominated by point tunneling. On the other hand, the thickness of the gate dielectric as well as the doping profile at the tunnel junction modifies the device performance. The gate-drain underlap is shown to reduce the ambipolar behavior of the devices without affecting their ON-characteristics. Very low variability is measured for the ON-current in the devices where BTBT dominates, while variability increases in the TAT region.

Lateral and vertical scaling of a QSA HBT for a 0.13/spl mu/m 200GHz SiGe:C BiCMOS technology

A 200 GHz F/sub t/ SiGe:C HBT has been integrated into a 0.13 /spl mu/m BiCMOS technology. A previous generation low complexity quasi self-aligned architecture (QSA) is scaled down both in a lateral and vertical way. Lateral sizing is obtained by using present-day step and scan tools. Vertical sizing is achieved by reducing the thermal budget of the active module and by an aggressive scaling of the SiGe:C base epitaxial layer. A deep trench module, featuring a thick oxide liner, has been developed. Excellent DC parameters and peak Ft/Fmax values of 200/160 GHz are demonstrated. The CMOS device characteristics remain unchanged by applying low thermal budget processing in the bipolar module.

Highly scalable bulk FinFET Devices with Multi-V T options by conductive metal gate stack tuning for the 10-nm node and beyond

A scalable multi-VT enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-VT is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack Tinv, JG, DIT and reliability as well as the device performance are shown to be unaffected by the multi VT process.

Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si<inf>45</inf>Ge<inf>55</inf>/Si cap deposition and the workfunction metal, high performance devices with balanced V<inf>t,sat</inf> (+0.12V, −0.16V) at scaled T<inf>inv</inf>∼1nm and gate length L<inf>g</inf>∼30nm are reported, leading to 17ps ring oscillators at 1µW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.

Experimental and computational investigation of concentration profiles of C1-C4 hydrocarbon radicals and molecules in low-pressure C2H2/O/H atomic flames at 600 K

In a synthesis of new insights in acetylene oxidation chemistry gained during the last decade, partly in this laboratory, a detailed reaction mechanism that can be schematized as Download : Download full-size image is put forward to explain the formation of reactive unsaturated C3-C4 species in low-pressure C2H2/O/H atomic flames. Concentration-versus-time profiles of HCCO, CH2, CH, C3H2, C2H, C3H4, and C4H2 were calculated on the basis of this mechanism and compared with experimental relative concentration profiles obtained by molecular beam sampling and threshold ionization mass spectrometry (MB-TIMS). This was done for data obtained in two different C2H2/O/H mixtures at 600 K and at a total pressure of 2 torr (≙98% He); absolute concentration profiles of C2H2, O, and H were also measured in these atomic flames. Both the shapes of the calculated profiles and the ratios of the calculated concentrations in the two mixtures are in excellent agreement with the measurements; only a few model parameters, involving C3H4 had to be adapted. Further confirmation of the proposed mechanism is provided by CH4-addition experiments, which also allow distinction between CH(2Π) and CH2(1A1) as dominant precursor of the C3 species. The manifest relevance to polyacetylene and aromatics production in hydrocarbon flames is discussed briefly.