Fausto Borghetti

A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck Converter

A single-inductor dual-output DC-DC buck converter is presented. The inductor, which is external, provides two independent output voltages ranging from 1.2V to the power supply with a maximum total output current of 200mA. The supply can range from 2.6 to 5V. The converter is fabricated in a 0.35mum p-substrate CMOS technology. Measurement results demonstrate that a peak power efficiency as high as 93.3% can be achieved and the efficiency is always >62.5%.

A 32x32-pixel array with in-pixel photon counting and arrival time measurement in the analog domain

A Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion is implemented in a 130-nm CMOS imaging technology. The proposed module is conceived for Single-Photon Avalanche Diode imagers and can operate both as a TAC or as an analog counter, thus allowing both time-correlated or time-uncorrelated imaging operation. A single-ramp, 8-bit ADC with two memory banks to allow high-speed, time-interleaved operation is also included within each module. A 32x32-TACs array has been fabricated with a 50-µm pitch in order prove the highly parallel operation and to test uniformity and power consumption issues. The measured time resolution (LSB) is of 160 ps on a 20-ns time range with a uniformity across the array within ±2LSBs, while DNL and INL are 0.7LSB and 1.9LSB respectively. The average power consumption is below 300µW/pixel when running at 500k measurements per second.

A 32×32 50ps resolution 10 bit time to digital converter array in 130nm CMOS for time correlated imaging

We report the design and characterisation of a 32×32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50µm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats.

A parallel 32×32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology

We report on the design and characterization of a 32 × 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at ± 0.4 and ±1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50µm in both directions and with a total TDC area of less than 2000µm2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).

A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.

A 160×128 single-photon image sensor with on-pixel 55ps 10b time-to-digital converter

Image sensors capable of resolving the time-of-arrival (ToA) of individual photons with high resolution are needed in several applications, such as fluorescence lifetime imaging microscopy (FLIM), Förster resonance energy transfer (FRET), optical rangefinding, and positron emission tomography. In FRET, for example, typical fluorescence lifetime is of the order of 100 to 300ps, thus deep-subnanosecond resolutions are needed in the instrument response function (IRF). This in turn requires new time-resolved image sensors with better time resolution, increased throughput, and lower costs. Solid-state avalanche photodiodes operated in Geiger-mode, or single-photon avalanche diodes (SPADs), have existed for decades [1] but only recently have SPADs been integrated in CMOS. However, as array sizes have grown, the readout bottleneck has also become evident, leading to hybrid designs or more integration and more parallelism on-chip [2,3]. This trend has accelerated with the introduction of SPAD devices in deep-submicron CMOS, that have enabled the design of massively parallel arrays where the entire photon detection and ToA circuitry is integrated on-pixel [4,5].

An integrated reset / pulse pile-up rejection circuit for pixel readout ASIC's

We present a compact and low power integrated circuit designed to control the reset and performs the pulse pile-up rejection in multi-channel spectroscopic-grade ASICs. The circuit has been implemented in 0.35 mum CMOS technology with an area of 60times80 mum2 and null static power consumption. These features makes this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X and gamma ray pixel detectors.

A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors

In this paper, a novel 10-bit A/D converter based on a pipeline-like architecture specific for low-noise, self-triggered sensors, (e.g., X-rays and 7-rays spectrometry) is presented. The main innovative feature of the proposed A/D structure is the concept that, for a sampled input signal, a pipeline ADC may behave as a combinatorial logic and may operate without any timing signal (clock). The conversion is obtained asynchronously propagating the partial conversions and the residues through the various stages. This concept is validated by means of a prototype ADC fabricated in a standard 0.35 mum CMOS technology. The active area is 2.24 mm2, and it provides a conversion in 2.5 mus (i.e., it can operate with a 400 kS/s data rate) featuring an ENOB equal to 8.91.

A Complete Read-Out Channel With Embedded Wilkinson A/D Converter for X-Ray Spectrometry

This paper presents a complete read-out channel suitable for large arrays of X-ray detectors to be used for spectrometry applications in space. The system is fully integrated except for the X-ray detector. It basically consists of a front-end circuit for processing the detector signal, a Wilkinson A/D converter for the analog-to-digital conversion and the digital logic required to ensure the correct handshaking between all the blocks of the read-out channel. The system allows us to process the signal provided by the detector down to the final analog-to-digital conversion. All these functionalities are embedded in a single chip that, in its final version, will be bump-bonded to the matrix of X-ray detectors. The chip, designed in a 0.35 mum CMOS technology, achieves an input-referred noise of 34 erms - , consuming 0.9 mW from a 3.3 V power supply. The on-board A/D converter features 10 bits of resolution with a maximum conversion time of 210 mus. The INL and DNL of the whole read-out channel are equal to plusmn3.3 LSB and plusmn0.2 LSB, respectively.

Characterization of large-scale non-uniformities in a 20k TDC/SPAD array integrated in a 130nm CMOS process

With the emergence of large arrays of high-functionality pixels, it has become critical to characterize the performance non-uniformity of such arrays. In this paper we characterize a 160×128 array of complex pixels, each with a single-photon avalanche diode (SPAD) and a time-to-digital converter (TDC). A study of the arrays non-uniformities in terms of the timing resolution, jitter, and photon responsivity is conducted for the pixels at various illumination levels, temperatures, and other operating conditions. In the study we found that, in photon-starved operation, the TDCs exhibit a median resolution of 55ps and a standard deviation of 2 ps. The pixels show a median timing jitter of 140ps. Moreover, we measured negligible variations in photon responsivity while changing the number of active pixels. These findings suggest that the image sensor can be used in highly reliable, large-scale, time-correlated measurements of single photons for biological, molecular, and medical applications. The chip is especially valuable for time-resolved imaging, single-photon counting, and correlation-spectroscopy under many realistic operating conditions.