Vincenzo Ferragina

Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators

We propose a digital background adaptive calibration technique for correcting offset and gain mismatches in time-interleaved multipath analog-digital (A/D) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain mismatches among the paths only by processing the digital output, without interfering with the operation of the modulator. This solution is also effective for any other time-interleaved A/D converter topology. Simulation results on a high-performance four-path bandpass /spl Sigma//spl Delta/ modulator, operating on a 5-MHz band at a clock frequency of 320 MHz, demonstrate the effectiveness of the proposed calibration technique, which allows us to achieve significant improvements of the signal-to-noise ratio and the spurious-free dynamic range in the presence of mismatches.

A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.

An integrated reset / pulse pile-up rejection circuit for pixel readout ASIC's

We present a compact and low power integrated circuit designed to control the reset and performs the pulse pile-up rejection in multi-channel spectroscopic-grade ASICs. The circuit has been implemented in 0.35 mum CMOS technology with an area of 60times80 mum2 and null static power consumption. These features makes this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X and gamma ray pixel detectors.

A Complete Read-Out Channel With Embedded Wilkinson A/D Converter for X-Ray Spectrometry

This paper presents a complete read-out channel suitable for large arrays of X-ray detectors to be used for spectrometry applications in space. The system is fully integrated except for the X-ray detector. It basically consists of a front-end circuit for processing the detector signal, a Wilkinson A/D converter for the analog-to-digital conversion and the digital logic required to ensure the correct handshaking between all the blocks of the read-out channel. The system allows us to process the signal provided by the detector down to the final analog-to-digital conversion. All these functionalities are embedded in a single chip that, in its final version, will be bump-bonded to the matrix of X-ray detectors. The chip, designed in a 0.35 mum CMOS technology, achieves an input-referred noise of 34 erms - , consuming 0.9 mW from a 3.3 V power supply. The on-board A/D converter features 10 bits of resolution with a maximum conversion time of 210 mus. The INL and DNL of the whole read-out channel are equal to plusmn3.3 LSB and plusmn0.2 LSB, respectively.

Low-power 6-bit flash ADC for high-speed data converters architectures

The design of low-power, medium resolution flash converter is presented. The goal is to provide a basic cell with state-of-the art figure of merit thus permitting low-power data converter architectures with a more flexible use of flash ADC cells. The designed 6-bit flash uses interpolation and V/I converters that operate as preamplifier stage of latches. Circuit simulations show a figure of merit as low as 1.2 pj/conv-lev at 100-MS/s sampling frequency and 3.3-V analog supply voltage

Use of dynamic element matching in a multi-path sigma-delta modulator

This paper describes the use of dynamic element matching in a multi-bit, multi-path sigma-delta modulators. The technique achieves noise shaping and enables the use of elements with 0.5% mismatch. Simulation results at the behavioral and gate level shows the possibility to achieve an SNR as large as 85 dB and SFDR of 90 dB with a 320 MHz equivalent clock frequency.

A 12.4 ENOB Incremental A/D Converter for High-Linearity Sensors Read-Out Applications

In this paper a 13b incremental A/D converter for high-linearity sensors read-out applications is described and characterized. The incremental solution is preferred to traditional SigmaDelta architectures to simplify the decimator filter topology, which is actually a single bit digital accumulator. This leads to lower area occupancy and power consumption. The input signal, which can be connected either in single-ended or differential mode, is sampled by a resettable SC integrator, followed by a discrete time comparator, which selects the feedback signal. The silicon prototype has been designed in 0.35mum technology with a power supply of 3.3V and consumes 950muW with throughput rate of 120Hz. The measurements results show an ENOB of 12.41 bits. The chip area is 0.22mm2.

Implementation of a novel read-out strategy based on a Wilkinson ADC for a 16/spl times/16 pixel X-ray detector array

In this paper we propose a Wilkinson type A/D converter as well as all the digital logic required for reading-out a 16/spl times/16 array of X-ray detectors. The proposed A/D converter architecture and read-out strategy allows us to handle an event rate as large as 10/sup 6/ event/s over the whole array and 10/sup 4/ event/s over the single row of the array with a resolution of 10 bits, consuming only 77 mW from a 3.3 V power supply. The A/D converter and the logic are embedded in an ASIC to be bump-bonded on top of the detector, which includes also the front-end electronics required for processing the sensor output signals. This work was done within the framework of an ESA research activity.

A Programmable 10b up-to-6MS/s SAR-ADC Featuring Constant-FoM with On-Chip Reference Voltage Buffers

A 10bit SAR-ADC implemented in a 1.2V 0.13mum CMOS with 1VppdiffFS, based on capacitive-charge redistribution can be programmed with Fs up-to-6MS/s, guaranteeing an ENOB>9b with a SFDR>74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoMap1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200muW and the FoMap0.1pJ/conv. This appears an attractive solution for embedded ADC

A CMOS 2D Micro-Fluxgate Earth Magnetic Field Sensor with Digital Output

A complete CMOS integrated microsystem for detecting the direction of the Earths magnetic field (whose full-scale value is on the order of 60muT), realized with the micromodule approach, including both sensor and electronic interface circuit, achieves 4deg accuracy on the measured angle and provides a digital output. The system response is linear in the range of plusmn60muT with a maximum non-linearity error of about 3% of full-scale.