Fausto Pellandini

Adaptive color image compression based on visual attention

This paper reports an adaptive still color image compression method which produces automatically selected ROI with a higher reconstruction quality with respect to the rest of the input image. The ROI are generated on-the fly with a purely data-driven technique based on visual attention. Inspired from biological vision, the multicue visual attention algorithm detects the most visually salient regions of an image. Thus, when operating in systems with low bit rate constraints, the adaptive coding scheme favors the allocation of a higher number of bits to those image regions that are more conspicuous to the human visual system. The compressed image files produced by this adaptive method are fully compatible with the JPEG standard, which favors their widespread utilization.

GSM speech coding and speaker recognition

This paper investigates the influence of GSM speech coding on text independent speaker recognition performance. The three existing GSM speech coder standards were considered. The whole TIMIT database was passed through these coders, obtaining three transcoded databases. In a first experiment, it was found that the use of GSM coding degrades significantly the identification and verification performance (performance in correspondence with the perceptual speech quality of each coder). In a second experiment, the features for the speaker recognition system were calculated directly from the information available in the encoded bit stream. It was found that a low LPC order in GSM coding is responsible for most performance degradations. By extracting the features directly from the encoded bit-stream, we also managed to obtain a speaker recognition system equivalent in performance to the original one which decodes and reanalyzes speech before performing recognition.

Efficient compressed domain target image search and retrieval

In this paper we introduce a low complexity and accurate technique for target image search and retrieval. This method, which operates directly in the compressed JPEG domain, addresses two of the CBIR challenges stated by The Benchathlon Network regarding the search of a specific image: finding out if an exact same image exists in a database, and identifying this occurrence even when the database image has been compressed with a different coding bit-rate. The proposed technique can be applied in feature-containing or featureless image collections, and thus it is also suitable to search for image copies that might exist on the Web for law enforcement of copyrighted material. The reported method exploits the fact that the phase of the Discrete Cosine Transform coefficients contains a significant amount of information of a transformed image. By processing only the phase part of these coefficients, a simple, fast, and accurate target image search and retrieval technique is achieved.

Discrete cosine transform chip for real-time video applications

A new implementation of a flexible discrete cosine transform (DCT) chip is presented. The DCT chip is suitable for transforming real-time video images using 16-point*16-point subframes. Some special features of distributed arithmetic and an application-specific pipelined RAM memory are used to obtain a high-performance architecture. A full system for 2-D 16-point*16-point transforms is integrated on a single chip using a 2- mu m CMOS technology. The choice of a DCT algorithm, the architecture, and the implementation are examined.<<ETX>>

Adaptive block-size transform coding for image compression

In this paper we report the results of an adaptive block-size transform coding scheme that is based on the sequential JPEG algorithm. This minimum information-overhead method implies a transform coding technique with two different block sizes: N/spl times/N and 2N/spl times/2N pixels. The input image is divided into blocks of 2N/spl times/2N pixels and each of these blocks is classified according to its image activity. Depending on this classification, either four N-point or a single 2N-point 2-D DCT is applied on the block. The purpose of the algorithm is to take advantage of large uniform regions that can be coded as a single large unit instead of four small units-as it is made by a fixed block-size scheme. For the same reconstruction quality, the results of the adaptive algorithm show a significant improvement of the compression ratio with respect to the non-adaptive scheme.

VLSI systems for image compression: a power-consumption/image-resolution trade-off approach

Low power consumption is a requirement for any battery powered portable equipment. When designing ASICs for image and video compression, emphasis has been placed mainly on building circuits that are fast enough to satisfy the high data throughput associated with image and video processing. The imminent development of portable systems featuring full multimedia applications, adds the low-power constraint to the design of VLSI circuits for this kind of application. Several techniques such as lowering the supply voltage, architectural parallelization, pipelining etc., have been proposed in the literature to achieve low-power consumption. In this paper we report a VLSI circuit featuring a power management user-controllable technique that trades image quality for power consumption in a transform-based algorithm.

High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware

The principles of high level modeling of digital hardware circuits using the extended timing diagrams (ETD) formalism, which adds conditions, events, action expressions, and particular constraints to traditional timing diagrams, are described. Hierarchy and concurrency are also integrated so that a full top-down design becomes possible, enhancing at the same time the readability. While, for simulation purposes, the implementation of the formalism generates behavioral VHDL (VHSIC Hardware Description Language) models, a dedicated high-level translator generates VHDL code for synthesis. Both the ETD formalism and its implementation are part of MODES, a more complex modeling expert system including complementary editors.<<ETX>>

An 8-bit low-power ADC array for CMOS image sensors

The paper presents an original analog-to-digital converter (ADC) array meeting the constraining requirements in resolution, speed, size, and low power consumption of high-performance low-cost video cameras. The converter array is based on ADC cells relying on a cyclic redundant signed digit (RSD) algorithm supporting comparators with extended tolerance. A prototype ADC array composed of 32 converters was integrated in a 1 /spl mu/m CMOS process and tested. It is featuring an 8 bit resolution for an active area of 2.1 mm/sup 2/, and a power consumption of 4 mW at a sampling rate of 4.2 MS/s, with a voltage supply of 2.6 V. Typical DNL and INL values of -0.5/+0.2 and /spl plusmn/0.4 LSB, respectively, were measured for each ADC cell. Moreover, an overall SNR of 45 dB can be achieved with a digital off-chip offset compensation.

Modeling and Simulation of Electromechanical Transducers in Microsystems Using an Analogue Hardware Description Language

The analytical modeling and simulation of conservative electrostatic, electromagnetic and electrodynamic transducers found in microsystems using a non-linear lumped-parameter approach is presented in this paper. A comparison is made between this approach and the linearized equivalent circuit method. All models of transducers are written in HDL-A/sup TM/, a proprietary analogue hardware description language (HDL). System-level simulation is performed in the SPICE simulator using behavioral models of the transducers. Finally, a parameter extraction and HDL model generation tool for devices is presented.

Low-power digital image sensor for still-picture image acquisition

This article presents the design and realization of a CMOS digital image sensor optimized for button-battery powered applications. First, a pixel with local analog memory was designed, allowing efficient sensor global shutter operation. The exposure time becomes independent on the readout speed and a lower readout frequency can be used without causing image distortion. Second, a multi-path readout architecture was developed, allowing an efficient use of the power consumption in sub-sampling modes. These techniques were integrated in a 0.5 um CMOS digital image senor with a resolution of 648 by 648 pixels. The peak supply current is 7 mA for a readout frequency of 4 Mpixel/s at Vdd equals 3V. Die size is 55 mm2 and overall SNR is 55 dB. The global shutter performance was demonstrated by acquiring pictures of fast moving objects without observing any distortion, even at a low readout frequency of 4 MHz.