Federico Guanziroli

A 1 W 104 dB SNR Filter-Less Fully-Digital Open-Loop Class D Audio Amplifier With EMI Reduction

This paper presents the design and implementation of a high-performance fully-digital PWM DAC and switching output stage which can drive a speaker in portable devices, including cellular phones. Thanks to the quaternary pulse-width modulation scheme, filter-less implementation are possible. A pre-modulation DSP algorithm eliminates the harmonic distortion inherent to the employed modulation process, and an oversampling noise shaper reduces the modulator clock speed to facilitate the hardware implementation while keeping high-fidelity quality. Radiated electromagnetic field emission of the class D amplifier is reduced thanks to a clock spreading technique with only a minor impact on audio performance characteristics. Clock jitter effects on the audio amplifier performance are presented, showing very low degradation for jitter value up to a few nanoseconds. The digital section works with a 1.2 V power supply voltage, while the output switching stage and its driver are supplied from a high-efficiency DC-DC converter either at 3.6 V or 5 V. An output power of 0.5 W at 3.6 V and 1 W at 5 V over an 8 Ω load with efficiency (digital section included) of about 79% and 81%, respectively, has been achieved. The total harmonic distortion (THD) at maximum output level is about 0.2%, while the dynamic range is 104 dB A-weighted. The active area is about 0.94 mm2 in a 0.13 μm single-poly, five-metal, N-well digital CMOS technology with double-oxide option (0.5 μm minimum length).