Alberto Minuti

A 10-b 100-kS/s 1-mW General-Purpose ADC for Cellular Telephones

An on-demand general-purpose analog-to-digital converter (GPADC), which achieves a 10-b accuracy of up to 100-kS/s request rate, is presented. The GPADC can process single-ended signals with selectable input ranges up to the battery voltage. The range selection accuracy is 1 LSB. The DAC architecture presents the benefits of a differential approach while sampling single-ended input signals. Built-in reference buffer and oscillator are included. An external clock source is not needed; only a conversion request signal is necessary. Dedicated low-power design solutions have been introduced to reduce power consumption at the maximum conversion request speed to about 1 mW at a 2.0-V supply voltage. New design solutions have been introduced to comply with system-level requirements, such as scaling and shifting of the battery voltage, buffering low-frequency input signals with high source impedance, and to cope with the presence of input signals with voltage levels higher than the GPADC supply voltage when the battery is discharged. The active area is about 0.58 mm2 in a 0.35-μm single-poly 5-metal CMOS technology with a MIM capacitor option.

A portable redundancy algorithm for capacitive/resistive SAR A/D converters

An algorithm, which can be used to add redundancy to existing SAR A/D converters for improving their performance, is presented. It needs very small extra analog area and preserves the intrinsic immunity to metastability of a classical SAR algorithm. A 14b Successive Approximation Register (SAR) A/D Converter, equipped with this algorithm, has been designed in a 40nm CMOS process to be embedded in a System-on-Chip (SoC). Maximum DNL/INL of 1.4LSB/3.0LSB and an Effective Number of Bits (ENOB) of 12.0 have been measured.

A/D conversion of the battery voltage in advanced CMOS technologies

A circuit implementing area efficient voltage scaling and shifting operations tailored to the A/D conversion of the battery voltage has been designed to be integrated in a 40nm CMOS process with double oxide option. The active area is 0.03mm2, whereas typical power consumption is 267μW from a 3.6V battery cell.

1.05V on-request 10b General-Purpose ADC in 65nm digital CMOS technology

A 10b asynchronous General-Purpose ADC is designed at 1.05V supply and in a 65nm digital CMOS process to be embedded in modem/multimedia processors. A pseudo-differential DAC, a built-in reference buffer, and a noise reduction/error correction algorithm allow low voltage, low power operations with large noise or disturbance immunity.