Fekri Kharbash

Enabling sizing for enhancing the static noise margins

This paper suggests a transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating at low voltages. The method relies on upsizing the length (L) of all transistors uniformly, and balancing the voltage transfer curves (VTCs) for maximizing the static noise margins (SNMs). We use the most well-known CMOS gates (INV, NAND-2, NOR-2) for introducing the novel sizing method, as well as for validating the concept and evaluating its performances. The results show that sizing has not entirely exhausted its potential, allowing to go beyond the well established delay-power tradeoff, as sizing can increase SNMs by: (i) adjusting the threshold voltages (VTH) and their variations (σVTH); and (ii) balancing the VTCs. Simulation results show that this sizing method enables more reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which could operate correctly at very low supply voltages, hence leading to ultra-low voltage/power circuits.

On upsizing length and noise margins

This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNMs). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (Vth) exactly (leading to exact Ls); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that Vth and L change by ~2%, while SNMs increase by ~30% with power and energy being reduced ~10× and ~20× respectively.

Towards ultra-low voltage/power using unconventionally sized arrays of transistors

This paper puts forward an enabling transistor sizing scheme targeting classical CMOS gates when implemented in advanced technologies. It relies on the well-known CMOS inverter for introducing the novel sizing concepts as well as for preliminary simulations verifying these concepts and comparing the resulting performances. These preliminary simulations support the claim that sizing has yet some potential as allowing to not only tradeoff delay versus power (which is well established and has been done over many years), but more interestingly: (i) to shape the static noise margins (SNMs); (ii) to adjust the threshold voltages (VTH); and (iii) to also confine threshold voltage variations (σVTH). Such a sizing scheme can lead to highly reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which will operate correctly at the lowest possible voltages, hence potentially reaching new ultra-low voltage/power limits.

Low power and highly reliable gates using arrays of optimally sized transistors

This paper introduces an enabling transistor sizing method for classical CMOS gates in advanced technology nodes through simple examples. The well-known CMOS inverter is used here both for presenting the different sizing options as well as for simulations for weighting performances. These preliminary results show that sizing is far from exhausting its potential as still allowing to: (i) improve delay and power; (ii) increase the static noise margins (SNMs); (iii) modify threshold voltages (VTH); and also (iv) reduce VTH variations (σVTH).

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNMs). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (Vth) exactly (precise Ls) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (Vbs) for having a single Lopt for all transistors (as opposed to having two different Lopt, one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although Vth and L change by ~10%, by using Vbs we can still achieve very high SNMs, while additionally reducing power and energy to ~50%.

On Schmitt trigger and other inverters

This paper compares classical CMOS versus Schmitt trigger (ST) inverters (INVs), sized both conventionally as well as unconventionally. The reason is that ST INVs are using positive feedback (which leads to hysteresis) and are expected to exhibit much better static noise margins (SNMs) than classical CMOS INVs. That is why ST INVs are more reliable. Lately, quite a few papers have been looking at using ST INVs for implementing SRAMs focusing mainly on the ultra-low voltage/power application range. Here we are going to look at SNM, delay, power and power-delay-product over the whole voltage range for exploring the potential advantages ST could offer in advanced CMOS technology nodes, and better identify their application range.

When one should consider Schmitt trigger gates

This paper compares classical CMOS logic gates with their Schmitt trigger (ST) versions, when sized both conventionally as well as unconventionally. The reason for studying ST logic gates is due to their positive feedback which leads to hysteresis and, more importantly, to their better static noise margins (SNMs)-than classical CMOS logic gates. Obviously, the larger SNMs make ST logic gates less sensitive to noises and, hence, more reliable. While lately, quite a few papers have been looking at using ST design concepts for implementing more reliable SRAM bit cells, significantly less work has been targeting combinatorial logic. Here we are going to explore the whole voltage range and performance spectrum, for a better understanding of not only the SNMs and power consumptions (at different frequencies and voltage levels) of ST NAND-2 gate, but also of the delays (speeds) they could achieve. This should give a clearer picture of the advantages/disadvantages of ST for combinatorial logic in advanced CMOS technology nodes, and implicitly identify their application range.

Reliability enhanced SRAM bit-cells

Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.

On SRAM bit-cells once again

Noises and variations are ubiquitous, but are still being ill-understood and in most cases treated simplistically, leading in most cases to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to ultra-low voltage (ULV) SRAM cells. We will show that unconventionally sized SRAM cells achieve higher SNMs than classically sized SRAM cells (hence it is to be expected that they will work correctly at lower supply voltages).