Felix Buergin

Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 mu W/MHz versus 9.6 mu W/MHz for 0.18mum CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 muW/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 muW/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of V dd-to-ground paths also contributes to a significant decrease of static consumption.

29% Power Saving through Semi-Custom Standard Cell Re-Design in a Front-End for Hearing Aids

Two versions of a front-end circuit for hearing aids have been placed on the same die fabricated in 0.18¿m CMOS technology. The VHDL source code has been the same in either case. The difference has been in the set of standard cells made available to the synthesis tool. In the reference design, this has been a regular industrial cell library, while a few hand-crafted cells featuring transistors of minimum size have been added for the second design. Measurements on real silicon show that the second version saves about 30% of energy compared to the reference with about one quarter of all cells replaced by minimum drive versions.

Wireless Implant Communications for Biomedical Monitoring Sensor Network

Galvanic coupling provides a novel data transmission between sensor units for low frequency intra-body communication with electrodes attached to the human skin. In this work, that approach has been adapted to implantable miniaturized pills. A communication system for wireless data transmission in muscle tissue is developed capable of transmitting data on four channels concurrently with a throughput of 4.8kbit/s. The main focus is the future implantability of such a miniaturized system for medical long term surveillance of patients. To achieve this goal, circuit size, low power consumption and electrical safety have to be carefully considered. The implemented frequency division multiple access (FDMA) system works in the frequency range between 100 kHz and 250 kHz. Tests have been processed with 4 transmitters units. The system architecture features the possibility of migration into a single system-on-chip.

42% power savings through glitch-reducing clocking strategy in a hearing aid application

Glitches are responsible for a significant proportion of overall power dissipation in digital signal processing circuits. Activity-reduction techniques that involve an optimized clocking strategy have been applied to a front-end block in a DSP adaptive directional microphone for hearing aids. Functionally equivalent implementations, differing only in their clocking scheme, have been integrated on silicon in a 0.25 mum CMOS technology. Measurements and post-layout simulations confirm a 42% reduction over single-edge-triggered clocking with clock gating. An overall power dissipation of 20 muW (@ 1.4 V, 374 kHz) has been measured. This achievement has been made possible by combining two novel techniques: a multi-stage clock gating, and a symmetric two-phase level-sensitive clocking with glitch-aware re-distribution of data-path registers

A Self-Timed 16-bit Multiplier for Low-Power Low-Frequency Applications

A comprehensive study of spurious activity propagation, based on transistor-level simulations targeting a 0.18 CMOS process, is carried out in traditional multiplier architectures (Carry-Save, Carry-Save with Booth receding and Wallace tree). The results suggest to implement self-timed multipliers, i.e. multipliers in which partial products are triggered by an independent delay line: they have the property of suppressing unnecessary switching activity. They are discussed in terms of area occupation and, especially, power dissipation and Energy- Delay-Product (EDP). After that, a new self-timed multiplier architecture is introduced. Transistor-level simulations point out a dissipation of 2.0 muW/MHz against 4.8 muW/MHz of a recently published self-timed multiplier and 4.1 muW/MHz of the most efficient traditional architecture (Wallace), with a reduced 5% area overhead compared to the latter one.

A 2.7-/spl mu/W/MHz transmission-gate-based 16-bit multiplier for digital hearing aids

Various 16-bit multiplier architectures are compared in terms of dissipated energy, EDP (energy-delay product), and area occupation, in view of low-power low-voltage signal processing for digital hearing aids and similar applications. It is found that the propagation of glitches along uneven and reconvergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save and other traditional array multipliers (5.4 to 6.1muW/MHz versus 9.4muW/MHz and more for 0.25mum CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates, a new approach is proposed to further improve the energy-efficiency (2.7muW/MHz), beyond recently published low-power architectures. Beside the reduction of the overall capacitance, transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching

Two-Phase Resonant Clocking for Ultra-Low-Power Hearing Aid Applications

Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k transistors and more than 2500 latches, has been designed, fabricated and tested. The measured energy con sumption of the design at 0.8 V is 62μW/MHz, about 7.5% less than the conventional single-edge-triggered benchmark. Closer analysis reveals that much of the energy savings brought about by resonant clocking at low supply voltages are lost when a CMOS circuit is operated at higher voltages. This is because of the crossover currents that persist for much of a clock period when a circuit is driven from sine-type clock waveform.

Low-power constant-coefficient FIR filtering in a hearing aid application

A new constant-coefficient FIR filter architecture is hereby presented, specifically designed for a VLSI adaptive directional microphone for hearing aids. Gate-level simulations targeting a 0.25 mum process point out relevant power savings compared to both the fully time-shared reference design (-80%) and a recently published low-power circuit (-32%), with a limited 11% area overhead compared to the latter one

Two-phase clocking combined with sleep transistors reduces active leakage in low-frequency portable applications

The aggressive down-scaling in semiconductor devices implies the transistor voltage threshold reduction, which is associated with an exponential increase in sub-threshold leakage currents. For this reason, static power consumption is becoming the major issue of the newer technologies. A novel low-leakage technique (2Phi+sleep), which combines level-sensitive two-phase clocking (2Phi) with sleep transistors (sleep), is proposed and compared to the state of the art. The results of transistor- level simulations indicate that the proposed technique reduces active leakage (-22% in the evaluated design in a 90 nm process), while preserving the same capabilities of counteracting stand-by leakage as conventional sleep transistors.

A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication

In this paper, resonant clocking is applied to a Viterbi decoder for ultra-low-power WLAN communication. Clock skew balancing and excessive cross-over currents are identified as the most relevant issues: H-clock-trees and a new latch circuit are proposed as innovative power-efficient design solutions. The chip has been integrated in a 0.25 μm CMOS process. Supplied at 1.75 V, the 1.35 mm2 core dissipates 50 mW at 54 Mb/s throughput, with about 27% power savings compared to an equivalent circuit with conventional one-phase single-edge-triggered (SET) clocking strategy and a recently published competitor by C.C. Lin, et al (2005). The chip works up to 77 MHz.