Felix Tarköy

Probability propagation and decoding in analog VLSI

The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes.

Decoding in analog VLSI

The iterative decoding of state-of-the-art error correcting codes such as turbo codes is computationally demanding. It is argued that analog implementations of such decoders can be much more efficient than digital implementations. This article gives a tutorial introduction to research on this topic. It is estimated that analog decoders can outperform digital decoders by two orders of magnitude in speed and/or power consumption.

Iterative multi-user decoding for asynchronous users

An iterative scheme for decoding asynchronous users on a multi-user adder channel is presented. In each iteration step, one users a posteriori symbol probabilities are computed. The contribution of that user to the sum signal is partially cancelled such that the residual noise is minimized. Simulations show that two rate-2/3 users of a noiseless binary adder channel can be separated by a 4-state code.

An analog VLSI decoding technique for digital codes

Iterative decoding of high-performance error-correcting codes, such as turbo and related codes, is computationally demanding. This paper presents the application of a new type of analog computing network that enables the construction of all-analog decoders for such codes which outperform digital decoders in terms of speed and/or power consumption. The analog networks are based on the observation that certain computations with probabilities are naturally carried out by elementary transistor circuits. As an illustrative example, a complete decoder circuit for a simple tail-biting trellis code is given. Practical implementation issues such as device and thermal mismatch are also discussed.

High-speed interfaces for analog, iterative VLSI decoders

The design of various high-speed interface architectures for off-chip connections to and from analog, iterative VLSI decoders is discussed. It is shown that for applications with high transmission rates and low to medium accuracy, MOSFET-only R-2R ladders in combination with switched-current memory cells are ideally suited, due to their current mode nature as well as their power and area efficiency. It is expected that data rates well above 100 MS/s can be obtained.

Robust/lossy discretization in CDMA systems

Robust/lossy discretization (RLD) alleviates the synchronization problem for code-division multiple-access (CDMA) systems at the expense of a small performance penalty. From the received signal, a low-pass filter removes high-frequency components that bear little information about the transmitted data. Discretization is achieved by sampling the resulting signal. To evaluate the performance of RLD, an expression for the sum information rate is derived. RLD is shown to be less sensitive to the spectral properties of the transmitted signal than matched-filter discretization and works well in CDMA systems.<<ETX>>