Felix Lustenberger

Probability propagation and decoding in analog VLSI

The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes.

Decoding in analog VLSI

The iterative decoding of state-of-the-art error correcting codes such as turbo codes is computationally demanding. It is argued that analog implementations of such decoders can be much more efficient than digital implementations. This article gives a tutorial introduction to research on this topic. It is estimated that analog decoders can outperform digital decoders by two orders of magnitude in speed and/or power consumption.

An analog VLSI decoding technique for digital codes

Iterative decoding of high-performance error-correcting codes, such as turbo and related codes, is computationally demanding. This paper presents the application of a new type of analog computing network that enables the construction of all-analog decoders for such codes which outperform digital decoders in terms of speed and/or power consumption. The analog networks are based on the observation that certain computations with probabilities are naturally carried out by elementary transistor circuits. As an illustrative example, a complete decoder circuit for a simple tail-biting trellis code is given. Practical implementation issues such as device and thermal mismatch are also discussed.

On mismatch errors in analog-VLSI error correcting decoders

A new type of nonlinear analog transistor networks has recently been proposed for turbo decoding of error correcting codes. However, the influence of various nonidealities on the performance of such analog decoders is not yet well understood. The paper addresses the performance degradation due to transistor mismatch. Some analytical results are derived that allow to compare the accuracy of analog decoders with that of digital decoders. Moreover, these results enable to incorporate transistor mismatch into fast high-level simulations.

Analog-decoder experiments with subthreshold CMOS soft-gates

A collection of analog soft-gate CMOS ASICs operating in subthreshold-mode was implemented in a low-cost semi-custom 0.8 /spl mu/m technology. These soft-gates allow, in particular, the realization of various decoders for simple error correcting codes on the breadboard level. Measurement results are presented for an (8,4,4) Hamming code.

High-speed interfaces for analog, iterative VLSI decoders

The design of various high-speed interface architectures for off-chip connections to and from analog, iterative VLSI decoders is discussed. It is shown that for applications with high transmission rates and low to medium accuracy, MOSFET-only R-2R ladders in combination with switched-current memory cells are ideally suited, due to their current mode nature as well as their power and area efficiency. It is expected that data rates well above 100 MS/s can be obtained.

A Universal Method for Hierarchical Object Recognition based on Low-Power Vision Sensors

A universal software framework for hierarchical object recognition has been devised based on V. B. Mountcastles observation (Mountcastle, 1978) that the human cortex consists of the same basic functionality which is used to subdivide the complex computations into elementary matching tasks, independently whether auditory, visual, olfactory, haptic or any other sensory information is presented at the input. Combined with a unique vision sensor system that is capable to directly extract contrast magnitude and direction, a powerful combination of hardware and software for real-time pattern-recognition tasks at very low power-consumption levels is presented

Battery powered high dynamic range vision system

A low cost autonomous vision system for real-time applications in natural environments has been realized. It encompasses a 160 by 128 pixel 120 dB dynamic range vision sensor performing contrast magnitude and direction computation at the pixel level (Ruedi, 2003), a BF 533 BlackFin processor, memory and a low data rate RF link usable to communicate the high level information extracted from the scene to a network of such devices. Used to implement a road marking detection algorithm, it proved to perform reliably at 25 frames per second in highly changing conditions ranging from night to sun in the field of view