Fengying Qiao

A high efficiency CMOS charge pump for low voltage operation

A high efficiency CMOS charge pump suitable for low voltage applications is proposed. To improve the pumping efficiency, the charge pump circuit employs a novel charge transfer switch (CTS) control scheme which combines the backward control scheme with the forward control scheme. In 130nm CMOS process, the simulation results have shown that the proposed charge pump has higher pumping efficiency compared to other charge pumps1.

Reliability Comparison of ISSG Oxide and HTO as Tunnel Dielectric in 3-D–SONOS Applications

The reliability (endurance and retention) of tunnel oxide (grown and deposited oxide) of 3-D–SONOS devices is compared. Devices with grown tunnel oxide show better initial oxide quality, better fresh retention, and more robust endurance characteristics. Both devices show similar cycling degradation trend. The worse postcycling retention is due to tunnel oxide degradation leading to a fast initial loss of charge stored in generated tunnel oxide defects and a higher trap-assisted tunneling rate.

A novel soft error immunity SRAM cell

The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state.

A proper approach to characterize retention-after-cycling in 3D-Flash devices

We propose a procedure to evaluate retention-after-cycling in 3D-Flash devices. Proper comparison of retention transients requires the initial charging level to be as close as possible, but P/E cycling results in serious ID-VG degradation, preventing a consistent extraction of the threshold voltage. We introduce a test where a relaxation phase is added after cycling, consisting in baking samples for 24 hours at 200°C. This relaxation appears to anneal interface traps and to remove locally accumulated charge, restoring similar shape of ID-VG curves before and after cycling, hence allowing a proper comparison of retention of fresh and stressed devices.

A novel combination FN/BBHH erase scheme for scaled SONOS device

In this paper, a novel erase method combining Fowler-Nordheim (FN) and two-sided band to band hot hole (BBHH) erase schemes is proposed and applied in a Silicon-oxide-Nitride-Oxide-Nitride (SONOS) device with 4.5 nm thick bottom oxide, which can hardly be erased by FN tunneling. Results show that the new erase mechanism is promising for nanometer-scale SONOS memory especially when Oxide-Nitride-Oxide (ONO) stack has been optimized.

Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology

In this paper, we have studied the total ionizing dose (TID) radiation response up to 2 Mrad(Si) of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells and memory circuits, fabricated in a 130 nm complimentary metal-oxide-semiconductor (CMOS) SONOS technology. We explored the threshold voltage (VT) degradation mechanism and found that the VT shifts of SONOS cells depend on the charge state; simply programming the cell to a higher VT cannot compensate for the radiation induced VT loss. The off-state current (Ioff) increase in the SONOS cell is also studied in this paper. Both VT and Ioff degradation would affect the memory system. Read data failures are mainly caused by VT shifts under irradiation, and program and erase failures are mainly caused by increased Ioff, which overloads the charge pumping circuit. By varying the reference current, our 4 Mb NOR flash chip has the potential to survive a radiation dose of 1 Mrad(Si) in read mode.

Investigation of TID degradation of high voltage circuits in flash memory

The total ionizing dose (TID) radiation response of a flash memory circuit including high voltage (HV) periphery was studied. We show that functional failure of the charge pumps (CP) is mostly caused by an increased load current, due to radiation induced leakage current in the HV pass transistors. This leads to a failure to program/erase the array in turn.

TID characterization of 0.13µm SONOS cell in 4Mb NOR flash memory

In this paper, we investigate the TID response of 0.13μm SONOS cell with different charge states up to 2 Mrad(Si) and propose an improved model. Additionally, radiation experiment results show that IRD increase is the main reason for read error in the fabricated 4Mb flash memory chip.

A novel internal field enhanced retention degradation model for localized charge trapping memory device

A novel internal electric field enhanced retention model for localized charge trapping memory devices is proposed to explain the reliability degradation. According to the model, the excitation energy level distribution profiles of trapped holes after different P/E cycling stress are demonstrated for the first time.

Radiation hardened read circuit with high reliability for SOI based SONOS memory

A radiation hardened read circuit for a SONOS type EEPROM memory is designed in 0.6µm SOI process. Total dose radiation would cause large threshold voltage shifts of both memory cells and MOS transistors, hence degrades the reliability and performance of the sense amplifier. Compensation techniques for the sampling inverter and discharge path are proposed to achieve radiation hardness. Double branch precharge technique is developed to improve the read speed. As a result, the proposed sense amplifier is not sensitive to the radiation. Besides its high reliability, the proposed read circuit demonstrates high speed, achieving a sensing time of only 9.67ns.