Liyang Pan

Nonvolatile memory devices with high density ruthenium nanocrystals

The nonvolatile memory transistor devices with embedded ruthenium (Ru) nanocrystals (NCs) are fabricated in a compatible way with conventional complementary metal-oxide semiconductor technology. The rapid thermal annealing for the whole gate stacks is used to form Ru NCs in pre-existed SiO2 matrix. Monocrystal Ru NCs with high density (3×1012 cm−2), small size (2–3 nm), and good uniformity both in spatial distribution and morphology are elaborated. A substantial memory window of 3.5 V is obtained and explained by the charging and effects of Ru NCs. The mechanisms of work function engineering are also discussed in this paper.

Error Correction Codes and Signal Processing in Flash Memory

This chapter is to introduce NAND flash channel model, error correction codes (ECC) and signal processing techniques in flash memory. There are several kinds of noise sources in flash memory, such as random-telegraph noise, retention process, inter-cell interference, background pattern noise, and read/program disturb, etc. Such noise sources reduce the storage reliability of flash memory significantly. The continuous bit cost reduction of flash memory devices mainly relies on aggressive technology scaling and multi-level per cell technique. These techniques, however, further deteriorate the storage reliability of flash memory. The typical storage reliability requirement is that non-recoverable bit error rate (BER) must be below 10-15. Such stringent BER requirement makes ECC techniques mandatory to guarantee storage reliability. There are specific requirements on ECC scheme in NOR and NAND flash memory. Since NOR flash is usually used as execute in place (XIP) memory where CPU fetches instructions directly from, the primary concern of ECC application in NOR flash is the decoding latency of ECC decoder, while code rate and error-correcting capability is more concerned in NAND flash. As a result, different ECC techniques are required in different types of flash memory. In this chapter, NAND flash channel is introduced first, and then application of ECC is discussed. Signal processing techniques for cancelling cell-to-cell interference in NAND flash are finally presented.

A novel high-speed and low-power negative voltage level shifter for low voltage applications

A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130nm 1.5V/5V triple-well CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of −4.5V. Simulation results show that the switching delay and power consumption have been significantly reduced by roughly 62% and 65%, respectively. In addition, the proposed level shifter realizes a wide operation margin with a lower VDD compared to conventional implementations.

Hybrid aluminum and indium conducting filaments for nonpolar resistive switching of Al/AlOx/indium tin oxide flexible device

The nonpolar resistive switching characteristics of an Al/AlOx/indium tin oxide (ITO) device on a plastic flexible substrate are investigated. By analyzing the electron diffraction spectroscopy results and thermal coefficient of resistivity, it is discovered that the formation of aluminum and indium conducting filaments in AlOx film strongly depends on the polarity of the applied voltage. The metal ions arising from the Al and ITO electrodes respectively govern the resistive switching in corresponding operation polarity. After 104 times of mechanical bending, the device can perform satisfactorily in terms of resistance distribution, read sequence of high and low resistive states, and thermal retention properties.

Probing ferromagnetic/ferroelectric interfaces via spin wave resonance

The interfacial properties of the ferromagnetic (FM)/ferroelectric (FE) heterostructure La0.7Sr0.3MnO3/BaTiO3 (LSMO/BTO) have been investigated by employing spin wave resonance technique. In addition to the uniform ferromagnetic resonance, spin wave resonances with both body and surface wave modes are observed. The analysis on the spin wave spectrum in comparison with that of a La0.7Sr0.3MnO3 thin film suggests that the ferroelectric BaTiO3 layer not only modifies the in-plane bulk magnetic anisotropy of La0.7Sr0.3MnO3 but also induces surface spin pinning both in plane and out of plane. Moreover, a quantitative determination of spin wave exchange constant D is obtained from the spin wave spectrum at low temperature. Our study proves that spin wave resonance is a powerful tool to investigate the buried interfaces in ferromagnetic/ferroelectric heterostructures.

A high efficiency CMOS charge pump for low voltage operation

A high efficiency CMOS charge pump suitable for low voltage applications is proposed. To improve the pumping efficiency, the charge pump circuit employs a novel charge transfer switch (CTS) control scheme which combines the backward control scheme with the forward control scheme. In 130nm CMOS process, the simulation results have shown that the proposed charge pump has higher pumping efficiency compared to other charge pumps1.

Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application

Based on a novel two-dimension array architecture, a 1.8 V 0.44 mm2 1 Kbits embedded non-volatile random access memory (NVRAM) IP is developed with 0.18 mum standard logic CMOS process. Several high voltage solutions and circuits are proposed to improve the reliability and safety of the system. Furthermore, the power consumption for read and write operations are controlled under 312 muA and 88 muA respectively. The merits make it suitable for low power RFID application.

A Combined Modulation of Set Current With Reset Voltage to Achieve 2-bit/cell Performance for Filament-Based RRAM

A combined operation scheme to realize multibit switching in filament-based bipolar RRAM device is proposed. By combining the modulations of the current compliance in set operations with the stop voltage in reset operations together, the size or the quantity of the filaments in the film bulk can be controlled. An RRAM device with the structure of Ag/HfOx/Pt is fabricated and the 2-bit/cell memory function is achieved by the proposed modulation. Furthermore, the 2-bit/cell data reliability is satisfactory including the high-temperature retention, cycling endurance.

MLC nand flash retention error recovery scheme through word line program disturbance

Aggressive scaling down of Nand Flash induced serious reliability degeneration. Endurance and data retention lifetime deteriorated has become important scaling barrier. In this paper we propose a data retention reliability enhancing scheme through word line program disturbance (RE-WPD) for high scaled Nand Flash. The key ideal of RE-WPD is injecting extra electrons into floating gate through word line program disturbance, and recovers data retention errors due to floating gate charge leakage. As the result, 54% data retention bit error rate and 67% endurance improvement is achieved on commercial 2Xnm MLC Nand Flash.

An ultra-low-power extended counting ADC For large scale sensor arrays

In this paper, an ultra-low-power area-efficient 12-bit extended counting analog-to-digital conversion (EC-ADC) is presented. A double-sampling configuration for incremental ΣΔ modulators is proposed to halve the clock frequency of EC-ADC for the same conversion accuracy and rate. A class-AB operational transconductance amplifier (OTA) for low power EC-ADC is developed. The proposed architecture has been implemented using a commercial 0.18μm CMOS technology and occupies an area of 0.036mm2. Measured results show that a power consumption of 13μW can be achieved at the conversion rate of 50Ksamples/s and 10.2-bit accuracy respectively.