Fernand Boeri

Image processing on a SIMD/SPMD architecture: OPSILA

OPSILA, is a description given of a general-purpose parallel architecture with two different forms of parallelism: the well-known SIMD (single-instruction, multiple data shown), a synchronous form of parallelism; and SPMD (single program, multiple data stream), which is an asynchronous mode. It is shown that OPSILA is efficient for a wide variety of image algorithms including low and high level processing. The efficiency of OPSILA is demonstrated for the low-level algorithms, through the implementation of a set of typical operations: local (convolution), global (histogram), and geometric corrections.<<ETX>>

A partitioning algorithm for system-level synthesis

The partitioning/scheduling/allocation algorithm developed for the CAPSYS method is presented. The aim of this project is to define a tool able to automatically design dedicated and embedded VLIW architectures for large and complex applications. It inherits a sizable knowledge-pool from the wider field of parallel processors, VLIW compiler design and high-level synthesis. Emphasis is placed on constraints of such a system synthesis approach and more especially on the particularity of the partitioning step. The proposed solution implements a software/hardware approach based on the list-scheduling heuristic.<<ETX>>

OPSILA: a vector and parallel processor

A multiprocessor machine with two operating modes and simple synchronization mechanisms is discussed. The operating modes are the vector single-instruction multiple-data (SIMD) mode and the parallel single program stream, multiple data stream (SPMD) mode. Synchronizations are reduced to the switching between these two modes. Mixing these two operating modes offers the programmer a comfortable programming environment: vector parallelization is performed by the compiler and the hardware, and, since SPMD parallelization requires mainly the partitioning of the entire set of data, the synchronizations are then often obvious. >

Experience using a SIMD/SPMD multiprocessor architecture

Abstract Numerous applications require an ever increasing computational power, which is hardly be provided by classical sequential computers. Nowadays we are seeing the emergence of scientific computers which mix several schemes of parallelism. These new machines show that effecient implementation of applications are not straightforward due to hardware and software constrainsts. We consider in this paper a multiprocessor machine with two operating modes and with simple synchronization mechanisms. We study the implementation of several applications and we show that this machine allows an efficient handling of complex problems.

Automatic exploration of VLIW processor architectures from a designer's experience based specification

This paper presents a new synthesis approach for dedicated systems. The aim of the synthesis scheme is to achieve can automatic exploration of VLIW processor architectures from a pure C description of the input system. The innovation consists of the fact that unit allocation must manage the fact that a function may be realized either by dedicated functional units or by a set of lower-level efficiently controlled functional units. For example, execution of a square root function can be accomplished in two ways: either by a dedicated functional unit or by an oriented software implementation of Newtons iterations. The aim is to find the best global trade-off between all the candidate architectures. In order to illustrate this synthesis scheme, we give an example issued on a sonar application.<<ETX>>

Concurrent control systems: from Grafcet to VHDL

The automated production systems (APS) are composed of concurrent interacting entities, so any model should exhibit parallel and sequential behaviours. The Grafcet is now well established in manufacturing to specify the awaited behaviour of the APS. Moreover programmable components increase modularity and allow a higher integration rate of circuits. The paper studies the hardware implementation of a Grafcet specification into such a component. Those components have to be programmed using a hardware description language. We therefore focus on inherent problems of such an approach and we study different kinds of possible solutions to automatically translate a Grafcet specification into a VHDL program. In particular, we introduce a solution based on synchronous language works about symbolic research of stability states. This compiler only accepts the stable grafcets. In addition to automatically generating a VHDL code, this solution provides a way to check some safety properties on Grafcet.

Hardware architecture modelling using an object-oriented method

The very high integration rate and the increasing complexity of digital hardware architectures and embedded applications lead designers to search for new tools and methods. In order to reduce the time-to-market it becomes essential to allow designers to evaluate performances of a given application with the targetted architecture very soon in the design phase. So we have decided to build a modelling simulation environment in order to evaluate the requisite number of cycles for processing a given application with a simple model of a digital hardware architecture. Then, our main objective and the greatest part of our work is to describe this environment with an example based on the Pine DSP and some classical digital signal processing applications: FIR, FFT butterfly, Viterbis Butterfly.

Esterel and Java in an object-oriented modelling and simulation framework for heterogeneous software and hardware systems. The SEP approach

The size of todays digital systems is increasing very quickly. So design tools have to allow the maximum reusability and an adapted level of description depending on our goals during each part of the design cycle. Moreover, systems require more and more heterogeneous competency domain. Then we have to be able to manage the integration of complex and heterogeneous software and hardware systems. In some previous articles (F. Mallet et al., 1998), we presented an object oriented method and the related tool, which were demonstrated to be useful in order to model and simulate hardware digital architectures and their software applications in order to obtain performance estimations. The paper firstly intends to show the ease of integration into our framework of some capabilities to describe parts of system behaviour with other formalisms. Indeed, due to the description power of our generic object oriented model and without any modification, we managed to take care of components, the behaviour of which is described using the synchronous reactive language Esterel. Secondly, we illustrate the use of our new extensions to efficiently model an automatic control system for a sprinkler.

From program to hardware: A parallel architecture compiler

Abstract In this paper we present a method for designing synchronous parallel processors for dedicated applications. The specifications of the target application are the program itself and some hardware constraints. The method consists in compiling the specifications in order to provide an optimized architecture of a VLIW processor and the application object code. The goal of the optimization process is to maximize performances with respect to the hardware constraints. The architecture of the generic processor is such that each outcome processor may be integrated in a SIMD machine without re-compiling.

A comparison study of minimization methods of unit interconnection in VLIW processors

Abstract Previous studies have shown the significant part of the interconnection optimization in architecture synthesis. During this process, operator allocation to functional units is done, followed by a data path allocation phase which consists in minimizing the numbers of registers, multiplexers and physical links. We propose, in this paper, to describe briefly four methods to solve the data path allocation problem and to compare their efficiencies on scalar and vector algorithms. Three methods consist in already published techniques and the fourth is a new procedure based on the maximum compatible mechanism.