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Dive into the research topics where Fernando Avila-Herrera is active.

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Featured researches published by Fernando Avila-Herrera.


IEEE Journal of Photovoltaics | 2016

Organic Solar Cells Toward the Fabrication Under Air Environment

Victor S. Balderrama; Fernando Avila-Herrera; José Guadalupe Sánchez; Josep Pallarès; Osvaldo Vigil-Galán; L.F. Marsal; M. Estrada

In this work, we analyze the performance parameters of the inverted organic solar cells (OSC) partially fabricated under an air environment, comparing them with those of similar solar cells manufactured totally under a nitrogen environment. Both solar cells use PTB7 and PC70BM as the active blend layer. The electrical parameters were extracted from the current density-voltage characteristic (J-V) under light and dark conditions. At the beginning, the OSCs partially fabricated under an air environment showed a similar performance as those manufactured under an N2 environment. After 120 h, the power conversion efficiency of the OSCs partially fabricated under an air environment decreased 32% with respect to its initial value. The degradation process under the ISOS-D1 protocols was also analyzed.


joint international eurosoi workshop and international conference on ultimate integration on silicon | 2015

From double to triple gate: Modeling junctionless nanowire transistors

Bruna Cardoso Paz; Marcelo Antonio Pavanello; M. Cassé; Sylvain Barraud; Gilles Reimbold; O. Faynot; Fernando Avila-Herrera; A. Cerdeira

This paper presents a continuous, physically and charge-based new model for triple gate junctionless nanowire transistors (3G JNT). The presented model was evolved from a previous one designed for double gate junctionless transistors (2G JNT). The capacitance coupling and the internal potential changing from 2G to 3G JNTs are considered. The model validation is performed through both numerical simulation and experimental measurements for long and short channel devices.


ieee international autumn meeting on power electronics and computing | 2015

Proposal of compact analytical modeling for trigate junctionless nanowire transistors

Fernando Avila-Herrera; A. Cerdeira; M. Estrada; Bruna Cardoso Paz; Marcelo Antonio Pavanello

A compact analytical model for junctionless nanowire transistors is developed taking into account the fin height and including its capacitance. This model is based on a previous one for double-gate transistors just considering the dependence of the fin height and the short channel effects. The validation has been performed by 3D simulations for structures of 15 nm and 10 nm of height obtaining a very good agreement between modeled and simulated data.


Solid-state Electronics | 2015

Compact model for short-channel symmetric double-gate junctionless transistors

Fernando Avila-Herrera; A. Cerdeira; Bruna Cardoso Paz; M. Estrada; B. Iniguez; Marcelo Antonio Pavanello


Solid-state Electronics | 2016

Charge-based compact analytical model for triple-gate junctionless nanowire transistors

Fernando Avila-Herrera; Bruna Cardoso Paz; A. Cerdeira; M. Estrada; Marcelo Antonio Pavanello


Microelectronics Reliability | 2016

Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors

M. Estrada; M. Rivas; I. Garduno; Fernando Avila-Herrera; A. Cerdeira; Marcelo Antonio Pavanello; Israel Mejia; M. A. Quevedo-Lopez


Solid-state Electronics | 2014

Pseudo-Boltzmann model for modeling the junctionless transistors

Fernando Avila-Herrera; A. Cerdeira; J. B. Roldán; P. Sánchez-Moreno; I. M. Tienda-Luna; Benjamin Iniguez


Solid-state Electronics | 2017

Crystalline-like temperature dependence of the electrical characteristics in amorphous Indium-Gallium-Zinc-Oxide thin film transistors

M. Estrada; Y. Hernandez-Barrios; A. Cerdeira; Fernando Avila-Herrera; J. Tinoco; Oana Moldovan; Francois Lime; B. Iniguez


joint international eurosoi workshop and international conference on ultimate integration on silicon | 2018

Adaption of triple gate junctionless MOSFETs analytical compact model for accurate circuit design in a wide temperature range

A. Cerdeira; Fernando Avila-Herrera; M. Estrada; Rodrigo Trevisoli Doria; Marcelo Antonio Pavanello


Solid-state Electronics | 2017

A compact explicit DC model for short channel Gate-All-Around junctionless MOSFETs

Francois Lime; Fernando Avila-Herrera; A. Cerdeira; Benjamin Iniguez

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Bruna Cardoso Paz

Centro Universitário da FEI

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B. Iniguez

Rensselaer Polytechnic Institute

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Benjamin Iniguez

Université catholique de Louvain

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J. Tinoco

Universidad Veracruzana

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