I. Garduno
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Publication
Featured researches published by I. Garduno.
Semiconductor Science and Technology | 2011
Ghader Darbandy; Romain Ritzenthaler; Francois Lime; I. Garduno; M. Estrada; A. Cerdeira; Benjamin Iniguez
Gate-leakage current reduction is the key motivation for the replacement of traditional SiO2 gate insulator with alternative gate dielectrics. In this work, a guideline for the determination of the suitable high-k candidate was reported in the case of a SiO2/high-k gate stack in a nanoscale double-gate (DG) MOSFET. Analytical models of direct tunneling gate leakage current with SiO2 as an interfacial layer have been considered. Using these models, the most promising high-k materials for different conditions were predicted, considering the effects of equivalent oxide thickness (EOT), gate leakage current, electron effective mass, dielectric constant-k value, barrier height and interfacial oxide thickness.
Semiconductor Science and Technology | 2011
Ghader Darbandy; Francois Lime; A. Cerdeira; M. Estrada; I. Garduno; Benjamin Iniguez
In this paper, we use analytical models of the direct tunneling gate leakage current to determine the high-k dielectric suitable for the nanoscale ultra-thin body SOI MOSFET structure with the predicted equivalent oxide thickness (EOT) and the maximum value of gate leakage current according to the requirements of the latest ITRS roadmap for three technological nodes. The most important criteria for selecting alternative dielectrics (maximum gate leakage current, EOT, electron effective mass, dielectric constant k-value, barrier height and SiO2 thickness as an interfacial layer) were taken into account to determine the suitability of the gate oxide materials. In the ideal case without an interfacial layer, HfO2 and Lu2O3 were found to be the best gate oxide materials for the 17, 15 and 14 nm technological node requirements.
spanish conference on electron devices | 2007
E. Miranda; J.C. Tinoco; I. Garduno; M. Estrada; A. Cerdeira
In this work we examine the electrical behavior of thin (~10 nm) SiO2/TiO2 gate insulator stacks in MOS capacitors that have undergone multiple hard breakdown events. The post-breakdown current is modeled using a simple equivalent electrical circuit consisting of a diode with series and parallel resistances. We show that the current flowing through the non-damaged oxide area still plays a significant role even after breakdown. Similarities with previous studied systems are also discussed.
international caribbean conference on devices, circuits and systems | 2006
I. Garduno; P. Saint-Cast; J.C. Tinoco; M. Estrada
Recently we reported the possibility of using the room temperature plasma oxidation mechanism to obtain ultrathin silicon oxide films. The oxidation process in O2 and N2O can be modeled by power law dependence with time and is inversely proportional with pressure. On that work, the parameters that modeled the oxidation process were fitting parameters and were analyzed independently for each gas. In present work we derived a general expression to model plasma oxidation processes. In addition, the dependence of the oxidation rate with pressure and temperature were further specified so they are associated to physical mechanisms. Comparison of experimental curves with modeled, using this general expression, is presented
ieee international autumn meeting on power electronics and computing | 2015
M. Estrada; A. Cerdeira; V.S. Balderrama; I. Garduno; I. Hernandez; J. Tinoco; R. Picos; B. Iniguez
The dependence with the measurement frequency observed in the Capacitance-Voltage characteristics of Metal-Insulator-Semiconductor structures using an amorphous oxide semiconductor material is presented and analyzed. It is demonstrated by simulation that the effect is due to the Distribution of States (DOS) present in the energy gap of the semiconductor material and strongly depends on the capture cross section of the DOS.
international conference on ultimate integration on silicon | 2012
G. Darbandy; Jasmin Aghassi; J. Sedlmeir; Udit Monga; I. Garduno; A. Cerdeira; Benjamin Iniguez
This paper presents Double Gate (DG) MOSFET models of the temperature dependences as part of a compact analytical model for the direct tunneling gate leakage and Trap-Assisted-Tunneling (TAT) current. We compare the adapted modeling calculations with experimental data of the gate leakage current in Trigate MOSFETs at various temperatures. The results of the direct tunneling current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements with SiON as a gate oxide material. Our analysis above threshold voltage shows that the direct tunneling gate leakage current is clearly dominant over the TAT, while it is the opposite below threshold.
device research conference | 2010
Ghader Darbandy; Romain Ritzenthaler; Francois Lime; I. Garduno; M. Estrada; A. Cerdeira; Benjamin Iniguez
Solid-state Electronics | 2013
A. Cerdeira; I. Garduno; J. Tinoco; Romain Ritzenthaler; Jacopo Franco; Mitsuhiro Togo; T. Chiarella; Cor Claeys
Microelectronics Reliability | 2016
M. Estrada; M. Rivas; I. Garduno; Fernando Avila-Herrera; A. Cerdeira; Marcelo Antonio Pavanello; Israel Mejia; M. A. Quevedo-Lopez
Solid-state Electronics | 2013
Ghader Darbandy; Jasmin Aghassi; Josef Sedlmeir; Udit Monga; I. Garduno; A. Cerdeira; Benjamin Iniguez