Roy Winter

New method for determining flat-band voltage in high mobility semiconductors

The method that is commonly used for determining the flat-band voltage (VFB) and the flat-band capacitance (CFB) of metal oxide semiconductor (MOS) capacitors depends on many parameters and can only be used in the case of low interface trap density (Dit) when the capacitance–voltage measurements are carried out at high frequencies. This paper demonstrates a new and simple method for determining VFB and CFB. The method is based on the point of inflection in the capacitance–voltage curve. This method does not require the knowledge of material or experimental parameters and can be used on high Dit and high border trap density MOS structures at all frequencies.

Indium out-diffusion in Al2O3/InGaAs stacks during anneal at different ambient conditions

Indium out-diffusion during anneal enhances leakage currents in metal/dielectric/InGaAs gate stacks. In this work, we study the influence of ambient conditions during anneal on indium out-diffusion in Al2O3/InGaAs structures, prior to the gate metal deposition. Using X-ray photoemission spectroscopy and time of flight secondary ions mass spectrometry, we observed much lower indium concentrations in the Al2O3 layer following vacuum and O2 anneals compared to forming gas or nitrogen anneals. The electrical characteristics of the Ni/Al2O3/InGaAs gate stack following these pre-metallization anneals as well as after subsequent post metallization anneals are presented. Possible explanations for the role of the annealing ambient conditions on indium out-diffusion are presented.

Border trap reduction in Al2O3/InGaAs gate stacks

The effect of Al2O3 atomic layer deposition (ALD) temperature on the border trap density (Nbt) of Al2O3/InGaAs gate stacks is investigated quantitatively, and we demonstrate that lowering the trimethylaluminum (TMA)/water vapor ALD temperature from 270 °C to 120 °C significantly reduces Nbt. The reduction of Nbt coincides with increased hydrogen incorporation in low temperature ALD-grown Al2O3 films during post-gate metal forming gas annealing. It is also found that large-dose (∼6000 L) exposure of the In0.53Ga0.47As (100) surface to TMA immediately after thermal desorption of a protective As2 capping layer is an important step to guarantee the uniformity and reproducibility of high quality Al2O3/InGaAs samples made at low ALD temperatures.

Effects of Titanium Layer Oxygen Scavenging on the High-k/InGaAs Interface

One of the main challenges in the path to incorporating InGaAs based metal-oxide-semiconductor structures in nanoelectronics is the passivation of high-k/InGaAs interfaces. Here, the oxygen scavenging effect of thin Ti layers on high-k/InGaAs gate stacks was studied. Electrical measurements and synchrotron X-ray photoelectron spectroscopy measurements, with in situ metal deposition, were used. Oxygen removal from the InGaAs native oxide surface layer remotely through interposed Al2O3 and HfO2 layers observed. Synchrotron X-ray photoelectron spectroscopy has revealed a decrease in the intensity of InOx features relative to In in InGaAs after Ti deposition. The signal ratio decreases further after annealing. In addition, Ti 2p spectra clearly show oxidation of the thin Ti layer in the ultrahigh vacuum XPS environment. Using capacitance-voltage and conductance-voltage measurements, Pt/Ti/Al2O3/InGaAs and Pt/Al2O3/InGaAs capacitors were characterized both before and after annealing. It was found that the remote oxygen scavenging from the oxide/semiconductor interface using a thin Ti layer can influence the density of interface traps in the high-k/InGaAs interface.

Fermi level pinning in metal/Al2O3/InGaAs gate stack after post metallization annealing

The effect of post metal deposition annealing on the effective work function in metal/Al2O3/InGaAs gate stacks was investigated. The effective work functions of different metal gates (Al, Au, and Pt) were measured. Flat band voltage shifts for these and other metals studied suggest that their Fermi levels become pinned after the post-metallization vacuum annealing. Moreover, there is a difference between the measured effective work functions of Al and Pt, and the reported vacuum work function of these metals after annealing. We propose that this phenomenon is caused by charging of indium and gallium induced traps at the annealed metal/Al2O3 interface.

Characteristics of stress-induced defects under positive bias in high-k/InGaAs stacks

The introduction of InGaAs as a channel material for complementary metal-oxide-semiconductor technology presents major challenges in terms of the characterization of the various defects that affect the performance and reliability. Understanding the generation of defects by constant voltage stresses is crucial in terms of their concentration profiles and energy levels. In particular, we want to understand the real nature of the defects responsible for the dispersion of C-V in strong accumulation. Here, we show that the degradation under positive bias of metal/Al2O3/n-InGaAs capacitors reveals two contributions depending on the temperature that affects the C-V curves in a different way. Based on features of stressed C-V curves, it is possible to estimate the onset point of the distribution of border traps near the midgap condition. The results suggest that these defects are strongly related to the characteristics of the InGaAs substrate.

Investigation of stress induced interface states in Al2O3/InGaAs metal-oxide-semiconductor capacitors

Implementation of high-k dielectrics on InGaAs for CMOS technology requires capabilities to predict long-time degradation and the impact of process changes on degradation processes. In this work, the degradation under constant voltage stress of metal gate/Al2O3/InGaAs stacks is studied for n-type and p-type As2 passivated InGaAs substrates. The results show that the degradation for both positive bias and negative bias did not produce Al2O3 oxide traps, while the distribution of interface states increased. In particular, the distribution of interface states, calculated by the distributed impedance equivalent circuit model, increased significantly after positive bias stress regardless of the doping type of the substrate. The injection of carriers from the semiconductor conduction band into the gate dielectric enhanced the generation of interface states but not the generation of oxide traps, suggesting that the interfacial degradation is related primarily to the InGaAs surface and not to the oxide layer.

Effect of forming gas annealing on the degradation properties of Ge-based MOS stacks

The influence of forming gas annealing on the degradation at a constant stress voltage of multi-layered germanium-based Metal-Oxide-Semiconductor capacitors (p-Ge/GeOx/Al2O3/High-K/Metal Gate) has been analyzed in terms of the C-V hysteresis and flat band voltage as a function of both negative and positive stress fields. Significant differences were found for the case of negative voltage stress between the annealed and non-annealed samples, independently of the stressing time. It was found that the hole trapping effect decreases in the case of the forming gas annealed samples, indicating strong passivation of defects with energies close to the valence band existing in the oxide-semiconductor interface during the forming gas annealing. Finally, a comparison between the degradation dynamics of Germanium and III-V (n-InGaAs) MOS stacks is presented to summarize the main challenges in the integration of reliable Ge–III-V hybrid devices.The influence of forming gas annealing on the degradation at a constant stress voltage of multi-layered germanium-based Metal-Oxide-Semiconductor capacitors (p-Ge/GeOx/Al2O3/High-K/Metal Gate) has been analyzed in terms of the C-V hysteresis and flat band voltage as a function of both negative and positive stress fields. Significant differences were found for the case of negative voltage stress between the annealed and non-annealed samples, independently of the stressing time. It was found that the hole trapping effect decreases in the case of the forming gas annealed samples, indicating strong passivation of defects with energies close to the valence band existing in the oxide-semiconductor interface during the forming gas annealing. Finally, a comparison between the degradation dynamics of Germanium and III-V (n-InGaAs) MOS stacks is presented to summarize the main challenges in the integration of reliable Ge–III-V hybrid devices.

The Role of Catalyst Adhesion in ALD-TiO2 Protection of Water Splitting Silicon Anodes

Atomic layer deposited titanium dioxide (ALD-TiO2) has emerged as an effective protection layer for highly efficient semiconductor anodes which are normally unstable under the potential and pH conditions used to oxidize water in a photoelectrochemical cell. The failure modes of silicon anodes coated with an Ir/IrO x oxygen evolution catalyst layer are investigated, and poor catalyst/substrate adhesion is found to be a key factor in failed anodes. Quantitative measurements of interfacial adhesion energy show that the addition of TiO2 significantly improves reliability of anodes, yielding an adhesion energy of 6.02 ± 0.5 J/m2, more than double the adhesion energy measured in the absence of an ALD-TiO2 protection layer. These results indicate the importance of catalyst adhesion to an interposed protection layer in promoting operational stability of high efficiency semiconducting anodes during solar-driven water splitting.

The asymmetric band structure and electrical behavior of the GdScO3/GaN system

III–V nitrides are interesting materials for a very wide variety of electronic and optoelectronic devices. In this study, their interaction with GdScO3 (GSO), a ternary rare earth oxide, is investigated for MOS applications. We compare pulsed laser deposited amorphous and crystalline epitaxial GdScO3 in terms of their band alignment with the underlying GaN substrate and the resulting electrical characteristics of the MOS stack. The crystal structure of GdScO3 and GaN is investigated by means of x-ray diffraction, showing that crystalline oxide is growing epitaxially on GaN. X-ray photoelectron spectroscopy analysis shows a staggered band alignment with a GdScO3-GaN valence band offset of 3.6–3.7 eV, which is reflected in a very asymmetric current-voltage behaviour of the MOS capacitors: breakdown at positive bias, significantly earlier for the crystalline oxide (around 5 MV/cm) compared to the amorphous oxide (around 8 MV/cm), and no breakdown up to a field of −14 MV/cm at negative bias. Transmission elec...