Marcelino B. Santos

Low power BIST by filtering non-detecting vectors

In this paper, two techniques to reduce the energy and the average power consumption of the system are proposed. They are based on the fact that as the test progresses, the detection efficiency of the pseudo-random vectors decreases very quickly. Many of the pseudo-random vectors will not detect faults in spite of consuming a significant amount of energy from the power supply. In order to prevent this energy consumption, a filtering of the non-detecting vectors and a reseeding strategy are proposed.These techniques are evaluated on the set of ISCAS-85 benchmark circuits. Extensive simulations have been made using the SAIL energy simulator showing that, in large circuits, the energy consumption and the average power savings reach 90.0% with a mean value of 74.2% with the filtering technique, and 97.2% with an average value of 90.9% with the reseeding strategy.

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity

Low-power design looks for low-energy BIST. This paper considers the problem of minimizing the energy required to test a BISTed combinational circuit without modifying the stuck-at fault coverage and with no extra area or delay overhead over the classical LFSR architectures. The objective of this paper is twofold. First, is to analyze the impact of the polynomial and seed selection of the LFSR used as TPG on the energy consumed by the circuit. It is shown that appropriately selecting the seed of the LFSR can lead to an important energy reduction. Second, is to propose a method to significantly decrease the energy consumption of BIST sessions. For this purpose, a heuristic method based on a simulated annealing algorithm is briefly described in this paper. Experimental results using the ISCAS benchmark circuits are reported, showing variations of the weighted switching activity ranging from 147% to 889% according to the seed selected for the LFSR. Note that these results are always obtained with no loss of stuck-at fault coverage.

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors

This paper presents a new approach on aging sensors for synchronous digital circuits. An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems. The main advantage is that the sensors performance degradation works in favor of the predictive error detection. The sensor is out of the signal path. Performance error prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation. Such errors must not occur in safety-critical systems (automotive, health, space). A sensor insertion algorithm is also proposed, to selectively insert them in key locations in the design. Sensors can be always active or at pre-defined states. Simulation results are presented for a balanced pipeline multiplier in 65 nm CMOS technology, using Berkeley Predictive Technology Models (PTM). It is shown that the impact of aging degradation and/or PVT (Process, power supply Voltage and Temperature) variations on the sensor enhance error prediction.

Low-sensitivity to process variations aging sensor for automotive safety-critical applications

In this paper, circuit failure prediction by timing degradation is used to monitor semiconductor aging, which is a safety-critical problem in the automotive market. Reliability and variability issues are worsening with device scaling down. For safe operation, we propose on-chip, on-line aging monitoring. A novel aging sensor (to be selectively inserted in key locations in the design and to be activated from time to time) is proposed. The aging sensor is a programmable delay sensor, allowing decision-making for several degrees of severity in the aging process. It detects abnormal delays, regardless of their origin. Hence, it can uncover “normal” aging (namely, due to NBTI) and delay faults due to physical defects activated by long circuit operation. The proposed aging sensor has been optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Moreover, the area overhead of the new architecture is significantly less than the one of other aging sensors presented in the literature. Simulation results with a 65 nm sensor design are presented, ascertaining its usefulness and its low sensitivity, in particular to process variations.

Physical DFT for High Coverage of Realistic Faults

Test quality requires the ability of test patterns to cover realistic faults originated by physical defects induced during IC manufacturing. Recent progress in a methodology for physical testability analysis is reported in this paper. A refined bridging faults classification provides evidence that reconvergent fan-out areas should be carefully designed to avoid hard to detect faults. Moreover, the concept of selective decompaction is introduced, to show that with reduced area overhead, testability can significantly be increased. As a result, guidelines for cell library development, and for refined routing algorithms, are presented. The results are il1ustra.ted with several design examples. These examples also show that the realistic fault coverage can be higher or lower than the Line Stuck-At (LSA) fault coverage depending on the relative incidence of bridging and open faults, and the topological characteristics of the surrounding circuit.

Predictive error detection by on-line aging monitoring

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on users requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

Programmable aging sensor for automotive safety-critical applications

Electronic systems for safety-critical automotive applications must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is long-term performance degradation due to aging. For safe operation, aging monitoring should be performed on chip, namely using built-in aging sensors (activated from time to time). The purpose of this paper is to present a novel programmable nanometer aging sensor. The proposed aging sensor allows several levels of circuit failure prediction and exhibits low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Simulation results with a 65 nm sensor design are presented, that ascertain the usefulness of the proposed solution.

Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

The validation of high-quality tests requires Defect-Oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel tool, veriDOFS, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults. Design hierarchy is exploited by pre-computing a test view of each cell in a library. The good trade-off accuracy/tractability, as well as the computational efficiency of the new tool are demonstrated by means of structural benchmarks up to 100,000 transistors and 300,000 realistic faults.

Built-in aging monitoring for safety-critical applications

Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is to monitor long-term performance degradation due to aging in such harsh environments. For safe operation, or for preventive maintenance, it is desirable that such monitoring may be performed on chip. On-line built-in aging sensors (activated from time to time) can be an adequate solution for this problem. The purpose of this paper is to present a novel methodology for electronic systems aging monitoring, and to introduce a new architecture for an aging sensor. Aging monitoring is carried out by observing the degrading timing response of the digital system. The proposed solution takes into account power supply voltage and temperature variations and allows several levels of failure prediction. Simulation results are presented, that ascertain the usefulness of the proposed methodology.

High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies

In this paper, high voltage (HV) tolerant level-shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL). These level-shifters are tolerant to supply voltages higher than the process limit for individual CMOS transistors. The proposed HV DCVSL level shifters are particularly useful when it is mandatory to ensure a specific behavior during out of the normal mode periods (power up; power down; reset; etc.). These high voltage tolerant logic circuits were used in the power block of buck converter designed in a standard 3.3 V, 0.13 mum CMOS process, powered by an input voltage range from 2.7 V to 4.2 V.