Fernando Rodríguez-Salazar

Hamming hypermeshes: high performance interconnection networks for pin-out limited systems

Hypermeshes are promising candidates for the construction of high performance interconnection networks. Their main advantage is that they present a low diameter, high bandwidth, low latency network, which can naturally embed a wide range of communication patterns. Since a VLSI implementation of such a system is still far-off, we argue that any implementation is pin-out, rather than wire density limited. We will study the networks under this assumption. In this paper we introduce the Hamming hypermesh, which has a lower pin-out, in an attempt to enhance the performance of the network. It is shown both by theoretical work and simulations that this implementation outperforms previously proposed hypermeshes under the constant pin-out argument. Furthermore Hamming hypermeshes have the additional benefit of providing higher bandwidth channels and simpler switching structures. Since it has been shown that complete hypermeshes outperform the mesh, the torus, low dimensional k-ary n-cubes (with and without bypass channels), and multi-stage interconnection networks under the constant pin-out argument, it follows that incomplete hypermeshes outperform them as well.

Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops

In this work, we have analyzed the effects of variability, due to random dopant fluctuation (RDF), on the timing characteristics of flip-flops for the future technology generations of 25, 18, and 13 nm, based on extensive Monte Carlo simulations. The results show that RDF has a significant impact on all of the timing parameters and that these parameters do not follow a normal distribution; in particular, they are skewed and exhibit a large tail. Moreover, the dispersion and skewness of the timing parameters increase with technology scaling. The study of the exact shape of these distributions, especially in the tail section, is of fundamental importance in the design and modeling of high-performance, reliable, and economically feasible circuits. In this paper, the distribution tails are estimated based on simulation data, with the aid of statistical nonparametric probability density functions, and it has been found that timing distributions can better be represented by certain nonparametric distributions, in particular Pearson and Johnson systems. The use of these representations during the statistical static timing analysis will provide more accurate results as compared with the normal approximation of distributions and will eventually reduce the probability of yield loss.

Wireless Channel Model Based on SoC Design Methodology

In this paper, a new method to model and simulate a wireless communication system based on System on Chip design methodology will be presented. The network performance effected by the amount of detail in the simulation model. Hence there is a need to develop suitable abstractions that maintain the accuracy of the simulation while keeping the computational resource requirements low. The integration of communication modelling into the design modelling has been shown by modelling a noisy communication channel in SystemC. The channel supports different modulation techniques such as, Amplitude-shift keying, Phase-shift keying, Quadrature amplitude modulation. It supports the setting of different Signal to noise ratio and different types of interference for Point-to-Point and Point-to-Multipoint platforms based on SystemC design methodology.

RTL-level modeling of an 8B/10B encoder-decoder using SystemC

This paper presents an RTL-level model of an 8B/10B encoder/decoder block in SystemC. The use of 8B/10B coding is an important technique in the construction of high performance serial interfaces. These are particularly suitable for alleviating the I/O bottleneck of state of the art systems (which are pinout, rather than bandwidth limited). SystemC has been chosen because it provides a homogeneous design flow for complex designs (i.e. SoC and IP based design), where system modeling at the early stages of the design becomes increasingly important.

Optimization of on-chip link performance under area, power and variability constraints

A large number of repeaters are used in the global interconnects of any System-on-Chip (SoC) design for improving the delay characteristics, and these repeaters consume a significant portion of the chip area and power. In this work we emphasize that due to increasing trend of the variability, power and area optimal repeater insertion methodologies should also consider performance variability. Analytical models for area, power, performance and probability of link failure have been presented in terms of the size of the repeaters and inter-repeater segment length. It has been found that beyond a certain reduction in the size of the repeaters, the delay variability may exceed acceptable limits while still satisfying other constraints. For instance, with only 4% of performance loss due to the use of smaller repeaters, almost 30% of power and 40% of area savings can be achieved; however performance certainty is reduced by 24%. Therefore, while optimizing area, power and performance of on-chip communication links, delay (and power) variability should also be included in the figure of merit.

Wireless extension into existing SystemC design methodology

SystemC is established as a suitable design and modelling language. It provides a consistent methodology for the design and refinement of complex digital systems. This paper focuses on how wireless features can be incorporated into existing SystemC design methodology in order to use this methodology to model wireless systems. The SystemC modelling language currently lacks a standard framework that supports modelling of wireless communication systems (particularly the use of wireless communication channels). Three components must be investigated in order to achieve this target: the development of a system level model of a digital wireless communication channel that represents the core of any communication system, the creation of a small library of dedicated elements at system level, such as PLL (Phased Locked Loop), 8B/10B Encoder/Decoder and several communication protocols modelling, and a case study/demonstration validating wireless extension methodology. The first two parts have been modelled successful, so we now focus on modelling a flocking behaviour system and demonstrating how these parts integrate to achieve the target.

Measuring and Optimising Convergence and Stability in Terms of System Construction in SystemC

The current SystemC modelling language lacks a standard framework that supports the modelling of wireless communication systems. This research investigates how wireless features can be incorporated into existing SystemC design methodology. The components to be investigated in order to achieve this target are divided into three parts: developing a system-level model of a digital wireless communication channel, creating a small library of dedicated elements at system level, and concluding with a case study on flocking behaviour system to validate the wireless extension methodology. In previous works, all these parts were successfully modelled and implemented. In this paper, the integration of communication modelling is introduced into design modelling during the early stages of system development. We use a flocking behaviour system to show how the stability of the system and converging point are measured and optimised in terms of system construction, using some important concepts of graph theory.

Timing yield analysis of pipelined circuits under device variability

Due to continuous quest for greater throughput, pipelined circuits are used to support multi-cycle processing at greater clock frequencies, leaving limited design margins. Under statistical device variations, the delay distributions of the pipeline stages follow a skewed distribution in highly scaled devices. Therefore, in order to determine the maximum operating frequency of the pipelined circuits, accurate estimation of the slowest pipeline stage will have to be determined. This study shows that identifying the slowest pipeline stage using Clarks approximation [5] will produce quite optimistic results and will lead to significant yield loss. Moreover, it has been shown that while estimating the yield, the stage delay distributions in both low-to-high and high-to-low transitions need to be considered and hold time distributions should also be considered along with setup time distributions.

Modeling of Flocking Behaviour System in SystemC

This paper introduces the integration of communication modelling into design modelling during the early stages of system development. It presents the modelling of flocking behaviour system in SystemC, which is emerging as a suitable language for designing and modelling. SystemC provides a consistent methodology for the design and refinement of complex digital systems. In this paper, a demonstrator implementing communication between particles has been constructed and incorporated into the entire design methodology. The communication has been implemented through the incorporation of a wireless channel that was previously modelled.