Khaled Elgaid

50-nm T-gate metamorphic GaAs HEMTs with f/sub T/ of 440 GHz and noise figure of 0.7 dB at 26 GHz

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies.

Scaling of pseudomorphic high electron mobility transistors to decanano dimensions

The performance enhancement associated with the scaling of pseudomorphic high electron mobility transistors (PHEMTs) to deep decanano dimensions is studied using Monte Carlo (MC) simulations. The full scaling of a standard 120 nm PHEMT to gate lengths of 90, 70, 50 and 30 nm in both lateral and vertical dimensions is compared with an approach where only the lateral dimensions are scaled. The study is based on an extended transport module integrated in the finite element MC simulator H2F and accurate up to an electric field of 200 kV/cm, and on the careful calibration of MC device simulations against I–V characteristics from the real 120-nm gate length PHEMT. The fully scaled devices exhibit a continuous improvement in transconductance as channel lengths reduce while performance deteriorates in devices scaled only laterally. The contact resistances become a limiting factor to the performance of the fully scaled devices at shorter channel lengths. The microwave performance of the scaled devices is studied using the transient MC analysis.

Low-Hydrogen-Content Silicon Nitride Deposited at Room Temperature by Inductively Coupled Plasma Deposition

A novel room-temperature inductively coupled plasma chemical vapour deposition (ICP–CVD) technique has been developed, which yielded high-quality silicon nitride (SiN) films with a hydrogen content of less than 3 at. %. The chemical composition and bonding of the films were analysed by energy dispersive X-ray (EDX) analysis, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), and Fourier transform infrared spectroscopy (FTIR). The film optical indexes measured by ellipsometry were well correlated with film composition. Very little plasma-induced damage was observed on Van de Pauw samples of GaAs-based high-electron-mobility transistor (HEMT) layer structures grown by molecular beam epitaxy (MBE). Breakdown electric field >4×106 V cm-1 was observed for an ultrathin 5 nm room-temperature-grown ICP–CVD SiN film embedded in a metal-insulator-metal (MIM) capacitor structure. This technique has been successfully incorporated into the III–V MMIC process flow to provide significant flexibility towards realising array-based MMICs.

40 to 90 GHz impedance-transforming CPW Marchand balun

It is shown analytically that impedance-transforming planar Marchand baluns can be designed. A GaAs monolithic CPW balun, transforming between a 50 /spl Omega/ source impedance and 160 /spl Omega/ load terminations has been realised to demonstrate the technique. The balun operates from 40 to 90 GHz with excellent performance.

Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs

Abstract Based on careful calibration in respect of 70 nm n-type strained Si channel Si/SiGe modulation doped FETs (MODFETs) fabricated by Daimler Chrysler, numerical simulations have been used to study the impact of the device geometry and various doping strategies on device performance and linearity. Both the lateral and vertical layer structures are crucial to achieve high RF performance or high linearity. The simulations suggest that gate length scaling helps to achieve higher RF performance, but degrades the linearity. Doped channel devices are found to be promising for high linearity applications. Trade-off design strategies are required for reconciling the demands of high device performance and high linearity simultaneously.

Design and characterization of elevated CPW and thin film microstrip structures for millimeter-wave applications

A new family of low loss series/shunt matching stub structures, based on a CPW/thin film microstrip combination using an MMIC airbridge approach to realize an elevated transmission line, is presented. This airbridge approach to elevate the CPW centre conductor and thin-film microstrip line was developed to achieve low losses in the millimeter-wave frequency band with a wide impedance range. By elevating lines from the substrate, the dielectric loss can be reduced. We achieve high impedance with a lower attenuation level than conventional CPW and low impedance with an air-substrate thin-film microstrip. Experimental results are presented in support of the novel structures.

Modelling of InP HEMTs with high indium content channels

Performance of sub-100 nm InP HEMTs with various indium contents in the channel is studied using an ensemble Monte Carlo device simulator. A detail insight into the non-equilibrium electron transport in the InGaAs channel is reported.

High Performance GaN High Electron Mobility Transistors on Low Resistivity Silicon for

This letter reports the RF performance of a 0.3-μm gate length AlGaN/AlN/GaN HEMT realized on a 150-mm diameter low-resistivity (LR) (σ <; 10 Ω · cm) silicon substrate. Short circuit current gain (f_T) and maximum frequency of oscillation (f_MAX) of 55 and 121 GHz, respectively, were obtained. To our knowledge, these are the highest f_T/f_MAX values reported to date for GaN HEMTs on LR silicon substrates.

X

We previously reported a procedure for the fabrication of high electron mobility transistors (HEMTs) using nanoimprint lithography [Y. Chen et al., Microelectron. Eng. 67,68, 189 (2003)] to produce T-shaped gates with 120 nm foot widths. The most recent batch of transistors fabricated by this original procedure had a peak transconductance of 450 mS/mm and fT of 40 GHz. In this article we describe a number of refinements to the original process with the main aims to improve performance and yield of devices. The work had two parallel strands. The first involved the development of improved silicon stamping tools to limit resist trenching effects and to produce stamping tools with smaller foot widths. T-shaped tools with 50 nm foot widths were produced from this work. The second strand of work was to optimize various aspects of transistor design and the imprint conditions used to fabricate gates which resulted in pHEMTs with a peak transconductance of 480 mS/mm and an fT of 75 Ghz.

-Band Applications

Approximate analytical formulae are presented for calculating the characteristic impedance of elevated coplanar waveguides (CPWs). In such a structure, both the signal and ground traces are suspended above a substrate using airbridge technology. The analysis of this structure is formulated in terms of partial capacitances obtained through conformal mapping techniques. The paper highlights the limitations of previously published formulae. Furthermore, the paper presents a method to overcome these limitations over a limited range of practical geometries. Comparisons between measured, simulated, and calculated results are included, and excellent agreement is obtained for a wide range of geometries. In addition, the effects of CPW-to-elevated coplanar waveguide transitions and supporting posts on the characteristics of elevated lines are analyzed. Good agreement is obtained for a relatively complex fabricated structure which is nonuniform at nine points in the direction of signal propagation. The fabrication of elevated CPW structures is also discussed.