Florian Bauer

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.

Layout options for stability tuning of SRAM cells in multi-gate-FET technologies

We present an investigation of different layout options for multi-gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static noise margins (SNM) of 210 mV have been measured at IV VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.

Analog design challenges and trade-offs using emerging materials and devices

Analog device figures-of-merit change significantly with the introduction of advanced materials and devices such as high-k or multiple-gate FETs. Measurements show enhanced intrinsic gain and matching behavior for MuGFETs which help to reduce area and power consumption in analog circuits. However, high-k degrades matching, flicker noise and Vt stability. Measured device performance is used to simulate the impact of these trends on circuit design trade-offs. Migrating from SiON to HfO2 dielectric approximately doubles area and power consumption to keep matching and noise performance constant. Transient VT instabilities in the range of 10 mV can degrade the resolution of analog-to-digital converters by more than one bit. The use of non-binary ADCs is proposed to overcome these issues.

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.

Advances in Multi-Gate MOSFET Circuit Design

In this paper recent advances in multi-gate MOSFET (MuGFET) circuit design are reported. The feasibility of essential parts of low-power mobile SoC applications and large scale integration capability is shown. Excellent short channel control enables undoped metal gate MuGFETs to outperfom their planar counterparts in terms of delay-leakage trade-off. Superior voltage scaling efficiency and competitive performance is demonstrated for a product typical critical path. Design and layout optimization for improved SRAM cell stability is shown. Beneficial analog performance is exemplary demonstrated for an OpAmp. A potential degradation of ADC performance due to transient Vt mismatch is shown, the use of redundancy is proposed as countermeasure. Key RF building blocks are presented, MuGFET specific design issues are outlined. A comparison of different ESD elements yields a potential ESD protection scheme combining planar and MuGFET devices.

Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits

Energy dissipation, performance, and voltage scaling of Multi-Gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10 k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.

Low-Voltage Scaled 6T FinFET SRAM Cells

Planar bulk devices suffer from high random dopant fluctuations (RDF) when scaled down to sub-32 nm technology nodes. This is considered as a major roadblock for the integration of these devices in high density 6T SRAM cells [1, 2]. The increasing variation of transistor parameters like VT, ION, IOFF, etc., can result in a large variability in performance and power. The possibility of leaving the channels undoped and their excellent immunity against Short Channel Effects (SCE) favors the use of FinFET-based multi-gate devices [3] for these technology nodes.